161 lines
5.1 KiB
C
161 lines
5.1 KiB
C
/***************************************************************************
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* Copyright (C) 2011 by Julius Baxter *
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* julius@opencores.org *
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* *
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* Copyright (C) 2013 by Marek Czerski *
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* ma.czerski@gmail.com *
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* *
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* Copyright (C) 2013 by Franck Jullien *
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* elec4fun@gmail.com *
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* *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef OR1K_H
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#define OR1K_H
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <target/target.h>
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/* SPR groups start address */
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#define GROUP0 (0 << 11)
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#define GROUP1 (1 << 11)
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#define GROUP2 (2 << 11)
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#define GROUP3 (3 << 11)
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#define GROUP4 (4 << 11)
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#define GROUP5 (5 << 11)
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#define GROUP6 (6 << 11)
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#define GROUP7 (7 << 11)
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#define GROUP8 (8 << 11)
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#define GROUP9 (9 << 11)
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#define GROUP10 (10 << 11)
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/* OR1K registers */
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enum or1k_reg_nums {
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OR1K_REG_R0 = 0,
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OR1K_REG_R1,
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OR1K_REG_R2,
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OR1K_REG_R3,
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OR1K_REG_R4,
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OR1K_REG_R5,
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OR1K_REG_R6,
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OR1K_REG_R7,
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OR1K_REG_R8,
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OR1K_REG_R9,
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OR1K_REG_R10,
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OR1K_REG_R11,
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OR1K_REG_R12,
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OR1K_REG_R13,
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OR1K_REG_R14,
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OR1K_REG_R15,
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OR1K_REG_R16,
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OR1K_REG_R17,
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OR1K_REG_R18,
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OR1K_REG_R19,
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OR1K_REG_R20,
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OR1K_REG_R21,
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OR1K_REG_R22,
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OR1K_REG_R23,
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OR1K_REG_R24,
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OR1K_REG_R25,
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OR1K_REG_R26,
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OR1K_REG_R27,
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OR1K_REG_R28,
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OR1K_REG_R29,
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OR1K_REG_R30,
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OR1K_REG_R31,
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OR1K_REG_PPC,
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OR1K_REG_NPC,
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OR1K_REG_SR,
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OR1KNUMCOREREGS
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};
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struct or1k_jtag {
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struct jtag_tap *tap;
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int or1k_jtag_inited;
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int or1k_jtag_module_selected;
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uint8_t *current_reg_idx;
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struct or1k_tap_ip *tap_ip;
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struct or1k_du *du_core;
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struct target *target;
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};
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struct or1k_common {
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struct or1k_jtag jtag;
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struct reg_cache *core_cache;
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uint32_t core_regs[OR1KNUMCOREREGS];
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int nb_regs;
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struct or1k_core_reg *arch_info;
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};
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static inline struct or1k_common *
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target_to_or1k(struct target *target)
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{
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return (struct or1k_common *)target->arch_info;
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}
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struct or1k_core_reg {
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const char *name;
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uint32_t list_num; /* Index in register cache */
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uint32_t spr_num; /* Number in architecture's SPR space */
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struct target *target;
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struct or1k_common *or1k_common;
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const char *feature; /* feature name in XML tdesc file */
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const char *group; /* register group in XML tdesc file */
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};
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struct or1k_core_reg_init {
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const char *name;
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uint32_t spr_num; /* Number in architecture's SPR space */
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const char *feature; /* feature name in XML tdesc file */
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const char *group; /* register group in XML tdesc file */
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};
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/* ORBIS32 Trap instruction */
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#define OR1K_TRAP_INSTR 0x21000001
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enum or1k_debug_reg_nums {
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OR1K_DEBUG_REG_DMR1 = 0,
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OR1K_DEBUG_REG_DMR2,
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OR1K_DEBUG_REG_DCWR0,
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OR1K_DEBUG_REG_DCWR1,
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OR1K_DEBUG_REG_DSR,
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OR1K_DEBUG_REG_DRR,
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OR1K_DEBUG_REG_NUM
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};
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#define NO_SINGLE_STEP 0
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#define SINGLE_STEP 1
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/* OR1K Debug registers and bits needed for resuming */
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#define OR1K_DEBUG_REG_BASE GROUP6 /* Debug registers Base address */
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#define OR1K_DMR1_CPU_REG_ADD (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
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#define OR1K_DMR1_ST 0x00400000 /* Single-step trace */
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#define OR1K_DMR1_BT 0x00800000 /* Branch trace */
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#define OR1K_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
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#define OR1K_DSR_TE 0x00002000 /* Trap exception */
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/* OR1K Instruction cache registers needed for invalidating instruction
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* memory during adding and removing breakpoints.
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*/
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#define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2) /* IC Block Invalidate Register 0x2002 */
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#endif
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