b0759dfc53
From struct nand_flash_controller : - remove unused field register_commands; - remove field controller_ready, exported but never referenced. Remove dead code pointed by controller_ready. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
770 lines
24 KiB
C
770 lines
24 KiB
C
/***************************************************************************
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* Copyright (C) 2009 by Alexei Babich *
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* Rezonans plc., Chelyabinsk, Russia *
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* impatt@mail.ru *
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* *
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* Copyright (C) 2010 by Gaetan CARLIER *
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* Trump s.a., Belgium *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/*
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* Freescale iMX2* OpenOCD NAND Flash controller support.
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* based on Freescale iMX3* OpenOCD NAND Flash controller support.
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*/
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/*
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* driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
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* tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
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* "nand write # file 0", "nand verify"
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*
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* get_next_halfword_from_sram_buffer() not tested
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* !! all function only tested with 2k page nand device; imx27_write_page
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* writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
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* !! oob must be be used due to NFS bug
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include "mx2.h"
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#include <target/target.h>
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/* This permits to print (in LOG_INFO) how much bytes
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* has been written after a page read or write.
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* This is useful when OpenOCD is used with a graphical
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* front-end to estimate progression of the global read/write
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*/
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#undef _MX2_PRINT_STAT
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//#define _MX2_PRINT_STAT
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static const char target_not_halted_err_msg[] =
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"target must be halted to use mx2 NAND flash controller";
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static const char data_block_size_err_msg[] =
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"minimal granularity is one half-word, %" PRId32 " is incorrect";
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static const char sram_buffer_bounds_err_msg[] =
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"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
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static const char get_status_register_err_msg[] = "can't get NAND status";
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static uint32_t in_sram_address;
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static unsigned char sign_of_sequental_byte_read;
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static int initialize_nf_controller(struct nand_device *nand);
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static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value);
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static int get_next_halfword_from_sram_buffer(struct target * target,
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uint16_t * value);
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static int poll_for_complete_op(struct target * target, const char *text);
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static int validate_target_state(struct nand_device *nand);
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static int do_data_output(struct nand_device *nand);
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static int imx27_command(struct nand_device *nand, uint8_t command);
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static int imx27_address(struct nand_device *nand, uint8_t address);
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NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
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{
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struct mx2_nf_controller *mx2_nf_info;
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int hwecc_needed;
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int x;
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mx2_nf_info = malloc(sizeof(struct mx2_nf_controller));
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if (mx2_nf_info == NULL) {
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LOG_ERROR("no memory for nand controller");
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return ERROR_FAIL;
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}
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nand->controller_priv = mx2_nf_info;
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mx2_nf_info->target = get_target(CMD_ARGV[1]);
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if (mx2_nf_info->target == NULL) {
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LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
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return ERROR_FAIL;
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}
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if (CMD_ARGC < 3) {
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LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
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return ERROR_FAIL;
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}
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/*
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* check hwecc requirements
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*/
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hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
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if (hwecc_needed == 0)
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mx2_nf_info->flags.hw_ecc_enabled = 1;
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else
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mx2_nf_info->flags.hw_ecc_enabled = 0;
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mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
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mx2_nf_info->fin = MX2_NF_FIN_NONE;
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mx2_nf_info->flags.target_little_endian =
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(mx2_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
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/*
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* testing host endianess
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*/
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x = 1;
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if (*(char *) &x == 1)
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mx2_nf_info->flags.host_little_endian = 1;
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else
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mx2_nf_info->flags.host_little_endian = 0;
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return ERROR_OK;
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}
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static int imx27_init(struct nand_device *nand)
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{
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struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
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struct target *target = mx2_nf_info->target;
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int validate_target_result;
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uint16_t buffsize_register_content;
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uint32_t pcsr_register_content;
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int retval;
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uint16_t nand_status_content;
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/*
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* validate target state
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*/
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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target_read_u16(target, MX2_NF_BUFSIZ, &buffsize_register_content);
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mx2_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
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target_read_u32(target, MX2_FMCR, &pcsr_register_content);
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if (!nand->bus_width) {
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/* bus_width not yet defined. Read it from MX2_FMCR */
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nand->bus_width =
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(pcsr_register_content & MX2_FMCR_NF_16BIT_SEL) ? 16 : 8;
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} else {
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/* bus_width forced in soft. Sync it to MX2_FMCR */
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pcsr_register_content |=
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((nand->bus_width == 16) ? MX2_FMCR_NF_16BIT_SEL : 0x00000000);
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target_write_u32(target, MX2_FMCR, pcsr_register_content);
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}
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if (nand->bus_width == 16)
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LOG_DEBUG("MX2_NF : bus is 16-bit width");
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else
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LOG_DEBUG("MX2_NF : bus is 8-bit width");
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if (!nand->page_size) {
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nand->page_size =
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(pcsr_register_content & MX2_FMCR_NF_FMS) ? 2048 : 512;
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} else {
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pcsr_register_content |=
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((nand->page_size == 2048) ? MX2_FMCR_NF_FMS : 0x00000000);
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target_write_u32(target, MX2_FMCR, pcsr_register_content);
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}
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if (mx2_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
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LOG_ERROR("NAND controller have only 1 kb SRAM, so "
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"pagesize 2048 is incompatible with it");
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} else {
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LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
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}
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initialize_nf_controller(nand);
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retval = ERROR_OK;
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retval |= imx27_command(nand, NAND_CMD_STATUS);
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retval |= imx27_address(nand, 0x00);
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retval |= do_data_output(nand);
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if (retval != ERROR_OK) {
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LOG_ERROR(get_status_register_err_msg);
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return ERROR_FAIL;
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}
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target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
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if (!(nand_status_content & 0x0080)) {
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LOG_INFO("NAND read-only");
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mx2_nf_info->flags.nand_readonly = 1;
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} else {
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mx2_nf_info->flags.nand_readonly = 0;
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}
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return ERROR_OK;
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}
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static int imx27_read_data(struct nand_device *nand, void *data)
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{
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struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
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struct target *target = mx2_nf_info->target;
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int validate_target_result;
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int try_data_output_from_nand_chip;
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/*
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* validate target state
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*/
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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/*
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* get data from nand chip
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*/
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try_data_output_from_nand_chip = do_data_output(nand);
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if (try_data_output_from_nand_chip != ERROR_OK) {
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LOG_ERROR("imx27_read_data : read data failed : '%x'",
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try_data_output_from_nand_chip);
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return try_data_output_from_nand_chip;
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}
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if (nand->bus_width == 16)
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get_next_halfword_from_sram_buffer(target, data);
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else
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get_next_byte_from_sram_buffer(target, data);
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return ERROR_OK;
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}
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static int imx27_write_data(struct nand_device *nand, uint16_t data)
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{
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LOG_ERROR("write_data() not implemented");
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return ERROR_NAND_OPERATION_FAILED;
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}
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static int imx27_reset(struct nand_device *nand)
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{
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/*
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* validate target state
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*/
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int validate_target_result;
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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initialize_nf_controller(nand);
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return ERROR_OK;
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}
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static int imx27_command(struct nand_device *nand, uint8_t command)
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{
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struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
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struct target *target = mx2_nf_info->target;
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int validate_target_result;
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int poll_result;
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/*
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* validate target state
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*/
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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switch(command) {
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case NAND_CMD_READOOB:
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command = NAND_CMD_READ0;
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/* set read point for data_read() and read_block_data() to
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* spare area in SRAM buffer
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*/
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in_sram_address = MX2_NF_SPARE_BUFFER0;
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break;
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case NAND_CMD_READ1:
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command = NAND_CMD_READ0;
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/*
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* offset == one half of page size
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*/
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in_sram_address =
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MX2_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
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break;
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default:
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in_sram_address = MX2_NF_MAIN_BUFFER0;
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break;
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}
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target_write_u16(target, MX2_NF_FCMD, command);
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/*
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* start command input operation (set MX2_NF_BIT_OP_DONE==0)
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*/
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target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FCI);
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poll_result = poll_for_complete_op(target, "command");
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if (poll_result != ERROR_OK)
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return poll_result;
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/*
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* reset cursor to begin of the buffer
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*/
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sign_of_sequental_byte_read = 0;
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/* Handle special read command and adjust NF_CFG2(FDO) */
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switch(command) {
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case NAND_CMD_READID:
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mx2_nf_info->optype = MX2_NF_DATAOUT_NANDID;
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mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
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break;
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case NAND_CMD_STATUS:
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mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
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mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
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target_write_u16 (target, MX2_NF_BUFADDR, 0);
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in_sram_address = 0;
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break;
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case NAND_CMD_READ0:
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mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
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mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
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break;
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default:
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/* Ohter command use the default 'One page data out' FDO */
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mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
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break;
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}
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return ERROR_OK;
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}
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static int imx27_address(struct nand_device *nand, uint8_t address)
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{
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struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
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struct target *target = mx2_nf_info->target;
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int validate_target_result;
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int poll_result;
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/*
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* validate target state
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*/
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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target_write_u16(target, MX2_NF_FADDR, address);
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/*
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* start address input operation (set MX2_NF_BIT_OP_DONE==0)
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*/
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target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FAI);
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poll_result = poll_for_complete_op(target, "address");
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if (poll_result != ERROR_OK)
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return poll_result;
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return ERROR_OK;
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}
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static int imx27_nand_ready(struct nand_device *nand, int tout)
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{
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uint16_t poll_complete_status;
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struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
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struct target *target = mx2_nf_info->target;
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int validate_target_result;
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/*
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* validate target state
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*/
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validate_target_result = validate_target_state(nand);
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if (validate_target_result != ERROR_OK)
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return validate_target_result;
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do {
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target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
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if (poll_complete_status & MX2_NF_BIT_OP_DONE)
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return tout;
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alive_sleep(1);
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}
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while (tout-- > 0);
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return tout;
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}
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static int imx27_write_page(struct nand_device *nand, uint32_t page,
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uint8_t * data, uint32_t data_size, uint8_t * oob,
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uint32_t oob_size)
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{
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struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
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struct target *target = mx2_nf_info->target;
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int retval;
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uint16_t nand_status_content;
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uint16_t swap1, swap2, new_swap1;
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int poll_result;
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if (data_size % 2) {
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LOG_ERROR(data_block_size_err_msg, data_size);
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (oob_size % 2) {
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LOG_ERROR(data_block_size_err_msg, oob_size);
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return ERROR_NAND_OPERATION_FAILED;
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}
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if (!data) {
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LOG_ERROR("nothing to program");
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return ERROR_NAND_OPERATION_FAILED;
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}
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/*
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* validate target state
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*/
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retval = validate_target_state(nand);
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if (retval != ERROR_OK)
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return retval;
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in_sram_address = MX2_NF_MAIN_BUFFER0;
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sign_of_sequental_byte_read = 0;
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retval = ERROR_OK;
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retval |= imx27_command(nand, NAND_CMD_SEQIN);
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retval |= imx27_address(nand, 0); //col
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retval |= imx27_address(nand, 0); //col
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retval |= imx27_address(nand, page & 0xff); //page address
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retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
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retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
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target_write_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
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if (oob) {
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if (mx2_nf_info->flags.hw_ecc_enabled) {
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/*
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* part of spare block will be overrided by hardware
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* ECC generator
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*/
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LOG_DEBUG("part of spare block will be overrided "
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"by hardware ECC generator");
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}
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target_write_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
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oob);
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}
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//BI-swap - work-around of imx27 NFC for NAND device with page == 2kb
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target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
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if (oob) {
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LOG_ERROR("Due to NFC Bug, oob is not correctly implemented "
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"in mx2 driver");
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return ERROR_NAND_OPERATION_FAILED;
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}
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//target_read_u16 (target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
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swap2 = 0xffff; //Spare buffer unused forced to 0xffff
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new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
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swap2 = (swap1 << 8) | (swap2 & 0xFF);
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target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
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target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
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/*
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* start data input operation (set MX2_NF_BIT_OP_DONE==0)
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*/
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target_write_u16(target, MX2_NF_BUFADDR, 0);
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target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
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poll_result = poll_for_complete_op(target, "data input");
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if (poll_result != ERROR_OK)
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return poll_result;
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target_write_u16(target, MX2_NF_BUFADDR, 1);
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target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
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poll_result = poll_for_complete_op(target, "data input");
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if (poll_result != ERROR_OK)
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return poll_result;
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target_write_u16(target, MX2_NF_BUFADDR, 2);
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target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
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poll_result = poll_for_complete_op(target, "data input");
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if (poll_result != ERROR_OK)
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return poll_result;
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target_write_u16(target, MX2_NF_BUFADDR, 3);
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target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
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|
poll_result = poll_for_complete_op(target, "data input");
|
|
if (poll_result != ERROR_OK)
|
|
return poll_result;
|
|
|
|
retval |= imx27_command(nand, NAND_CMD_PAGEPROG);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
/*
|
|
* check status register
|
|
*/
|
|
retval = ERROR_OK;
|
|
retval |= imx27_command(nand, NAND_CMD_STATUS);
|
|
target_write_u16 (target, MX2_NF_BUFADDR, 0);
|
|
mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
|
|
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
|
|
retval |= do_data_output(nand);
|
|
if (retval != ERROR_OK) {
|
|
LOG_ERROR (get_status_register_err_msg);
|
|
return retval;
|
|
}
|
|
target_read_u16 (target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
|
|
if (nand_status_content & 0x0001) {
|
|
/*
|
|
* page not correctly written
|
|
*/
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
#ifdef _MX2_PRINT_STAT
|
|
LOG_INFO("%d bytes newly written", data_size);
|
|
#endif
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int imx27_read_page(struct nand_device *nand, uint32_t page,
|
|
uint8_t * data, uint32_t data_size, uint8_t * oob,
|
|
uint32_t oob_size)
|
|
{
|
|
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
|
|
struct target *target = mx2_nf_info->target;
|
|
int retval;
|
|
uint16_t swap1, swap2, new_swap1;
|
|
if (data_size % 2) {
|
|
LOG_ERROR(data_block_size_err_msg, data_size);
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
if (oob_size % 2) {
|
|
LOG_ERROR(data_block_size_err_msg, oob_size);
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
|
|
/*
|
|
* validate target state
|
|
*/
|
|
retval = validate_target_state(nand);
|
|
if (retval != ERROR_OK) {
|
|
return retval;
|
|
}
|
|
/* Reset address_cycles before imx27_command ?? */
|
|
retval = ERROR_OK;
|
|
retval |= imx27_command(nand, NAND_CMD_READ0);
|
|
|
|
retval |= imx27_address(nand, 0); //col
|
|
retval |= imx27_address(nand, 0); //col
|
|
retval |= imx27_address(nand, page & 0xff); //page address
|
|
retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
|
|
retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
|
|
retval |= imx27_command(nand, NAND_CMD_READSTART);
|
|
|
|
target_write_u16(target, MX2_NF_BUFADDR, 0);
|
|
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
|
|
retval = do_data_output(nand);
|
|
if (retval != ERROR_OK) {
|
|
LOG_ERROR("MX2_NF : Error reading page 0");
|
|
return retval;
|
|
}
|
|
//Test nand page size to know how much MAIN_BUFFER must be written
|
|
target_write_u16(target, MX2_NF_BUFADDR, 1);
|
|
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
|
|
retval = do_data_output(nand);
|
|
if (retval != ERROR_OK) {
|
|
LOG_ERROR("MX2_NF : Error reading page 1");
|
|
return retval;
|
|
}
|
|
target_write_u16(target, MX2_NF_BUFADDR, 2);
|
|
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
|
|
retval = do_data_output(nand);
|
|
if (retval != ERROR_OK) {
|
|
LOG_ERROR("MX2_NF : Error reading page 2");
|
|
return retval;
|
|
}
|
|
target_write_u16(target, MX2_NF_BUFADDR, 3);
|
|
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
|
|
retval = do_data_output(nand);
|
|
if (retval != ERROR_OK) {
|
|
LOG_ERROR("MX2_NF : Error reading page 3");
|
|
return retval;
|
|
}
|
|
//BI-swap - work-around of imx27 NFC for NAND device with page == 2k
|
|
target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
|
|
target_read_u16(target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
|
|
new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
|
|
swap2 = (swap1 << 8) | (swap2 & 0xFF);
|
|
target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
|
|
target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
|
|
|
|
if (data)
|
|
target_read_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
|
|
if (oob)
|
|
target_read_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
|
|
oob);
|
|
#ifdef _MX2_PRINT_STAT
|
|
if (data_size > 0) {
|
|
/* When Operation Status is read (when page is erased),
|
|
* this function is used but data_size is null.
|
|
*/
|
|
LOG_INFO("%d bytes newly read", data_size);
|
|
}
|
|
#endif
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int initialize_nf_controller(struct nand_device *nand)
|
|
{
|
|
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
|
|
struct target *target = mx2_nf_info->target;
|
|
uint16_t work_mode;
|
|
uint16_t temp;
|
|
/*
|
|
* resets NAND flash controller in zero time ? I dont know.
|
|
*/
|
|
target_write_u16(target, MX2_NF_CFG1, MX2_NF_BIT_RESET_EN);
|
|
work_mode = MX2_NF_BIT_INT_DIS; /* disable interrupt */
|
|
if (target->endianness == TARGET_BIG_ENDIAN) {
|
|
LOG_DEBUG("MX2_NF : work in Big Endian mode");
|
|
work_mode |= MX2_NF_BIT_BE_EN;
|
|
} else {
|
|
LOG_DEBUG("MX2_NF : work in Little Endian mode");
|
|
}
|
|
if (mx2_nf_info->flags.hw_ecc_enabled) {
|
|
LOG_DEBUG("MX2_NF : work with ECC mode");
|
|
work_mode |= MX2_NF_BIT_ECC_EN;
|
|
} else {
|
|
LOG_DEBUG("MX2_NF : work without ECC mode");
|
|
}
|
|
target_write_u16(target, MX2_NF_CFG1, work_mode);
|
|
/*
|
|
* unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
|
|
*/
|
|
target_write_u16(target, MX2_NF_BUFCFG, 2);
|
|
target_read_u16(target, MX2_NF_FWP, &temp);
|
|
if ((temp & 0x0007) == 1) {
|
|
LOG_ERROR("NAND flash is tight-locked, reset needed");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
/*
|
|
* unlock NAND flash for write
|
|
*/
|
|
target_write_u16(target, MX2_NF_FWP, 4);
|
|
target_write_u16(target, MX2_NF_LOCKSTART, 0x0000);
|
|
target_write_u16(target, MX2_NF_LOCKEND, 0xFFFF);
|
|
/*
|
|
* 0x0000 means that first SRAM buffer @0xD800_0000 will be used
|
|
*/
|
|
target_write_u16(target, MX2_NF_BUFADDR, 0x0000);
|
|
/*
|
|
* address of SRAM buffer
|
|
*/
|
|
in_sram_address = MX2_NF_MAIN_BUFFER0;
|
|
sign_of_sequental_byte_read = 0;
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value)
|
|
{
|
|
static uint8_t even_byte = 0;
|
|
uint16_t temp;
|
|
/*
|
|
* host-big_endian ??
|
|
*/
|
|
if (sign_of_sequental_byte_read == 0)
|
|
even_byte = 0;
|
|
|
|
if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
|
|
LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
|
|
*value = 0;
|
|
sign_of_sequental_byte_read = 0;
|
|
even_byte = 0;
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
} else {
|
|
target_read_u16(target, in_sram_address, &temp);
|
|
if (even_byte) {
|
|
*value = temp >> 8;
|
|
even_byte = 0;
|
|
in_sram_address += 2;
|
|
} else {
|
|
*value = temp & 0xff;
|
|
even_byte = 1;
|
|
}
|
|
}
|
|
sign_of_sequental_byte_read = 1;
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int get_next_halfword_from_sram_buffer(struct target * target,
|
|
uint16_t * value)
|
|
{
|
|
if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
|
|
LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
|
|
*value = 0;
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
} else {
|
|
target_read_u16(target, in_sram_address, value);
|
|
in_sram_address += 2;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int poll_for_complete_op(struct target * target, const char *text)
|
|
{
|
|
uint16_t poll_complete_status;
|
|
for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
|
|
target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
|
|
if (poll_complete_status & MX2_NF_BIT_OP_DONE)
|
|
break;
|
|
|
|
usleep(10);
|
|
}
|
|
if (!(poll_complete_status & MX2_NF_BIT_OP_DONE)) {
|
|
LOG_ERROR("%s sending timeout", text);
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int validate_target_state(struct nand_device *nand)
|
|
{
|
|
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
|
|
struct target *target = mx2_nf_info->target;
|
|
|
|
if (target->state != TARGET_HALTED) {
|
|
LOG_ERROR(target_not_halted_err_msg);
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
|
|
if (mx2_nf_info->flags.target_little_endian !=
|
|
(target->endianness == TARGET_LITTLE_ENDIAN)) {
|
|
/*
|
|
* endianness changed after NAND controller probed
|
|
*/
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int do_data_output(struct nand_device *nand)
|
|
{
|
|
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
|
|
struct target *target = mx2_nf_info->target;
|
|
int poll_result;
|
|
uint16_t ecc_status;
|
|
switch(mx2_nf_info->fin) {
|
|
case MX2_NF_FIN_DATAOUT:
|
|
/*
|
|
* start data output operation (set MX2_NF_BIT_OP_DONE==0)
|
|
*/
|
|
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info->optype));
|
|
poll_result = poll_for_complete_op(target, "data output");
|
|
if (poll_result != ERROR_OK)
|
|
return poll_result;
|
|
|
|
mx2_nf_info->fin = MX2_NF_FIN_NONE;
|
|
/*
|
|
* ECC stuff
|
|
*/
|
|
if ((mx2_nf_info->optype == MX2_NF_DATAOUT_PAGE) && mx2_nf_info->flags.hw_ecc_enabled) {
|
|
target_read_u16(target, MX2_NF_ECCSTATUS, &ecc_status);
|
|
switch(ecc_status & 0x000c) {
|
|
case 1 << 2:
|
|
LOG_INFO("main area readed with 1 (correctable) error");
|
|
break;
|
|
case 2 << 2:
|
|
LOG_INFO("main area readed with more than 1 (incorrectable) error");
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
break;
|
|
}
|
|
switch(ecc_status & 0x0003) {
|
|
case 1:
|
|
LOG_INFO("spare area readed with 1 (correctable) error");
|
|
break;
|
|
case 2:
|
|
LOG_INFO("main area readed with more than 1 (incorrectable) error");
|
|
return ERROR_NAND_OPERATION_FAILED;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case MX2_NF_FIN_NONE:
|
|
break;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct nand_flash_controller imx27_nand_flash_controller = {
|
|
.name = "imx27",
|
|
.nand_device_command = &imx27_nand_device_command,
|
|
.init = &imx27_init,
|
|
.reset = &imx27_reset,
|
|
.command = &imx27_command,
|
|
.address = &imx27_address,
|
|
.write_data = &imx27_write_data,
|
|
.read_data = &imx27_read_data,
|
|
.write_page = &imx27_write_page,
|
|
.read_page = &imx27_read_page,
|
|
.nand_ready = &imx27_nand_ready,
|
|
};
|