58 lines
1.9 KiB
INI
58 lines
1.9 KiB
INI
# Atheros AR71xx MIPS 24Kc SoC.
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# tested on PB44 refererence board
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adapter_nsrst_delay 100
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jtag_ntrst_delay 100
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reset_config trst_and_srst
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set CHIPNAME ar71xx
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jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
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set TARGETNAME $CHIPNAME.cpu
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target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
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$TARGETNAME configure -event reset-halt-post {
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#setup PLL to lowest common denominator 300/300/150 setting
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mww 0xb8050000 0x000f40a3 # reset val + CPU:3 DDR:3 AHB:0
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mww 0xb8050000 0x800f40a3 # send to PLL
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#next command will reset for PLL changes to take effect
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mww 0xb8050008 3 # set reset_switch and clock_switch (resets SoC)
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}
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$TARGETNAME configure -event reset-init {
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#complete pll initialization
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mww 0xb8050000 0x800f0080 # set sw_update bit
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mww 0xb8050008 0 # clear reset_switch bit
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mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass
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mww 0xb8050008 1 # set clock_switch bit
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sleep 1 # wait for lock
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# Setup DDR config and flash mapping
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mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0)
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mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8)
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mww 0xb8000010 8 # force precharge all banks
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mww 0xb8000010 1 # force EMRS update cycle
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mww 0xb800000c 0 # clr ext. mode register
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mww 0xb8000010 2 # force auto refresh all banks
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mww 0xb8000010 8 # force precharge all banks
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mww 0xb8000008 0x31 # set DDR mode value CAS=3
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mww 0xb8000010 1 # force EMRS update cycle
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mww 0xb8000014 0x461b # DDR refresh value
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mww 0xb8000018 0xffff # DDR Read Data This Cycle value (16bit: 0xffff)
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mww 0xb800001c 0x7 # delay added to the DQS line (normal = 7)
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mww 0xb8000020 0
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mww 0xb8000024 0
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mww 0xb8000028 0
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}
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# setup working area somewhere in RAM
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$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
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# serial SPI capable flash
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# flash bank <driver> <base> <size> <chip_width> <bus_width>
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