1481 lines
42 KiB
C
1481 lines
42 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "arm920t.h"
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#include <helper/time_support.h>
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#include "target_type.h"
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#include "register.h"
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#include "arm_opcodes.h"
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/*
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* For information about the ARM920T, see ARM DDI 0151C especially
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* Chapter 9 about debug support, which shows how to manipulate each
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* of the different scan chains:
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*
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* 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
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* 1 ... debugging; watchpoint and breakpoint status, etc; also
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* MMU and cache access in conjunction with scan chain 15
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* 2 ... EmbeddedICE
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* 3 ... external boundary scan (SoC-specific, unused here)
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* 4 ... access to cache tag RAM
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* 6 ... ETM9
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* 15 ... access coprocessor 15, "physical" or "interpreted" modes
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* "interpreted" works with a few actual MRC/MCR instructions
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* "physical" provides register-like behaviors.
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*
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* The ARM922T is similar, but with smaller caches (8K each, vs 16K).
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*/
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#if 0
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
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static int arm920t_read_cp15_physical(struct target *target,
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int reg_addr, uint32_t *value)
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{
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struct arm920t_common *arm920t = target_to_arm920(target);
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struct arm_jtag *jtag_info;
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struct scan_field fields[4];
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uint8_t access_type_buf = 1;
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uint8_t reg_addr_buf = reg_addr & 0x3f;
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uint8_t nr_w_buf = 0;
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jtag_info = &arm920t->arm7_9_common.jtag_info;
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jtag_set_end_state(TAP_IDLE);
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arm_jtag_scann(jtag_info, 0xf);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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fields[0].tap = jtag_info->tap;
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fields[0].num_bits = 1;
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fields[0].out_value = &access_type_buf;
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fields[0].in_value = NULL;
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fields[1].tap = jtag_info->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = NULL;
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fields[2].tap = jtag_info->tap;
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fields[2].num_bits = 6;
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fields[2].out_value = ®_addr_buf;
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fields[2].in_value = NULL;
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fields[3].tap = jtag_info->tap;
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fields[3].num_bits = 1;
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fields[3].out_value = &nr_w_buf;
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fields[3].in_value = NULL;
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jtag_add_dr_scan(4, fields, jtag_get_end_state());
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fields[1].in_value = (uint8_t *)value;
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jtag_add_dr_scan(4, fields, jtag_get_end_state());
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jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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jtag_execute_queue();
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LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
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#endif
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return ERROR_OK;
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}
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static int arm920t_write_cp15_physical(struct target *target,
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int reg_addr, uint32_t value)
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{
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struct arm920t_common *arm920t = target_to_arm920(target);
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struct arm_jtag *jtag_info;
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struct scan_field fields[4];
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uint8_t access_type_buf = 1;
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uint8_t reg_addr_buf = reg_addr & 0x3f;
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uint8_t nr_w_buf = 1;
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uint8_t value_buf[4];
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jtag_info = &arm920t->arm7_9_common.jtag_info;
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buf_set_u32(value_buf, 0, 32, value);
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jtag_set_end_state(TAP_IDLE);
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arm_jtag_scann(jtag_info, 0xf);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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fields[0].tap = jtag_info->tap;
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fields[0].num_bits = 1;
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fields[0].out_value = &access_type_buf;
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fields[0].in_value = NULL;
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fields[1].tap = jtag_info->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = value_buf;
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fields[1].in_value = NULL;
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fields[2].tap = jtag_info->tap;
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fields[2].num_bits = 6;
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fields[2].out_value = ®_addr_buf;
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fields[2].in_value = NULL;
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fields[3].tap = jtag_info->tap;
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fields[3].num_bits = 1;
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fields[3].out_value = &nr_w_buf;
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fields[3].in_value = NULL;
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jtag_add_dr_scan(4, fields, jtag_get_end_state());
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
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#endif
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return ERROR_OK;
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}
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static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
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uint32_t arm_opcode)
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{
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int retval;
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struct arm920t_common *arm920t = target_to_arm920(target);
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struct arm_jtag *jtag_info;
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struct scan_field fields[4];
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uint8_t access_type_buf = 0; /* interpreted access */
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uint8_t reg_addr_buf = 0x0;
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uint8_t nr_w_buf = 0;
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uint8_t cp15_opcode_buf[4];
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jtag_info = &arm920t->arm7_9_common.jtag_info;
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jtag_set_end_state(TAP_IDLE);
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arm_jtag_scann(jtag_info, 0xf);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
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fields[0].tap = jtag_info->tap;
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fields[0].num_bits = 1;
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fields[0].out_value = &access_type_buf;
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fields[0].in_value = NULL;
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fields[1].tap = jtag_info->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = cp15_opcode_buf;
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fields[1].in_value = NULL;
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fields[2].tap = jtag_info->tap;
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fields[2].num_bits = 6;
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fields[2].out_value = ®_addr_buf;
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fields[2].in_value = NULL;
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fields[3].tap = jtag_info->tap;
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fields[3].num_bits = 1;
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fields[3].out_value = &nr_w_buf;
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fields[3].in_value = NULL;
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jtag_add_dr_scan(4, fields, jtag_get_end_state());
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arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
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retval = arm7_9_execute_sys_speed(target);
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if (retval != ERROR_OK)
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return retval;
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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LOG_ERROR("failed executing JTAG queue");
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return retval;
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}
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return ERROR_OK;
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}
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static int arm920t_read_cp15_interpreted(struct target *target,
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uint32_t cp15_opcode, uint32_t address, uint32_t *value)
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{
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struct arm *armv4_5 = target_to_arm(target);
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uint32_t* regs_p[1];
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uint32_t regs[2];
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uint32_t cp15c15 = 0x0;
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struct reg *r = armv4_5->core_cache->reg_list;
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/* load address into R1 */
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regs[1] = address;
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arm9tdmi_write_core_regs(target, 0x2, regs);
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/* read-modify-write CP15 test state register
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* to enable interpreted access mode */
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arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
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jtag_execute_queue();
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cp15c15 |= 1; /* set interpret mode */
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arm920t_write_cp15_physical(target, 0x1e, cp15c15);
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/* execute CP15 instruction and ARM load (reading from coprocessor) */
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arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
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/* disable interpreted access mode */
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cp15c15 &= ~1U; /* clear interpret mode */
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arm920t_write_cp15_physical(target, 0x1e, cp15c15);
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/* retrieve value from R0 */
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regs_p[0] = value;
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arm9tdmi_read_core_regs(target, 0x1, regs_p);
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jtag_execute_queue();
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
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#endif
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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r[0].dirty = 1;
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r[1].dirty = 1;
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return ERROR_OK;
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}
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static
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int arm920t_write_cp15_interpreted(struct target *target,
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uint32_t cp15_opcode, uint32_t value, uint32_t address)
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{
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uint32_t cp15c15 = 0x0;
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struct arm *armv4_5 = target_to_arm(target);
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uint32_t regs[2];
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struct reg *r = armv4_5->core_cache->reg_list;
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/* load value, address into R0, R1 */
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regs[0] = value;
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regs[1] = address;
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arm9tdmi_write_core_regs(target, 0x3, regs);
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/* read-modify-write CP15 test state register
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* to enable interpreted access mode */
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arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
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jtag_execute_queue();
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cp15c15 |= 1; /* set interpret mode */
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arm920t_write_cp15_physical(target, 0x1e, cp15c15);
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/* execute CP15 instruction and ARM store (writing to coprocessor) */
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arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
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/* disable interpreted access mode */
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cp15c15 &= ~1U; /* set interpret mode */
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arm920t_write_cp15_physical(target, 0x1e, cp15c15);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
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#endif
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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r[0].dirty = 1;
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r[1].dirty = 1;
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return ERROR_OK;
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}
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// EXPORTED to FA256
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uint32_t arm920t_get_ttb(struct target *target)
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{
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int retval;
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uint32_t ttb = 0x0;
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if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
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return retval;
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return ttb;
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}
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// EXPORTED to FA256
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void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
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{
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uint32_t cp15_control;
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/* read cp15 control register */
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arm920t_read_cp15_physical(target, 0x2, &cp15_control);
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jtag_execute_queue();
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if (mmu)
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cp15_control &= ~0x1U;
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if (d_u_cache)
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cp15_control &= ~0x4U;
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if (i_cache)
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cp15_control &= ~0x1000U;
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arm920t_write_cp15_physical(target, 0x2, cp15_control);
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}
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// EXPORTED to FA256
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void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
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{
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uint32_t cp15_control;
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/* read cp15 control register */
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arm920t_read_cp15_physical(target, 0x2, &cp15_control);
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jtag_execute_queue();
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if (mmu)
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cp15_control |= 0x1U;
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if (d_u_cache)
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cp15_control |= 0x4U;
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if (i_cache)
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cp15_control |= 0x1000U;
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arm920t_write_cp15_physical(target, 0x2, cp15_control);
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}
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// EXPORTED to FA256
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void arm920t_post_debug_entry(struct target *target)
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{
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uint32_t cp15c15;
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struct arm920t_common *arm920t = target_to_arm920(target);
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/* examine cp15 control reg */
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arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
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jtag_execute_queue();
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LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
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if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
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{
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uint32_t cache_type_reg;
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/* identify caches */
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arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
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jtag_execute_queue();
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armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
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}
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arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
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arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
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arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
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/* save i/d fault status and address register */
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arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
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arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
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arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
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arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
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LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
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arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
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if (arm920t->preserve_cache)
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{
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/* read-modify-write CP15 test state register
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* to disable I/D-cache linefills */
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arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
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jtag_execute_queue();
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cp15c15 |= 0x600;
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arm920t_write_cp15_physical(target, 0x1e, cp15c15);
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}
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}
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// EXPORTED to FA256
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void arm920t_pre_restore_context(struct target *target)
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{
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uint32_t cp15c15;
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struct arm920t_common *arm920t = target_to_arm920(target);
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/* restore i/d fault status and address register */
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arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
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arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
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arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
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arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
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/* read-modify-write CP15 test state register
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* to reenable I/D-cache linefills */
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if (arm920t->preserve_cache)
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{
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arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
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jtag_execute_queue();
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cp15c15 &= ~0x600U;
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arm920t_write_cp15_physical(target, 0x1e, cp15c15);
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}
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}
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static const char arm920_not[] = "target is not an ARM920";
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static int arm920t_verify_pointer(struct command_context *cmd_ctx,
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struct arm920t_common *arm920t)
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{
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if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
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command_print(cmd_ctx, arm920_not);
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return ERROR_TARGET_INVALID;
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}
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return ERROR_OK;
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}
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/** Logs summary of ARM920 state for a halted target. */
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int arm920t_arch_state(struct target *target)
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{
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static const char *state[] =
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{
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"disabled", "enabled"
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};
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struct arm920t_common *arm920t = target_to_arm920(target);
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struct arm *armv4_5;
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if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
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{
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LOG_ERROR("BUG: %s", arm920_not);
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return ERROR_TARGET_INVALID;
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}
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armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
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arm_arch_state(target);
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LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
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state[arm920t->armv4_5_mmu.mmu_enabled],
|
|
state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
|
|
state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int arm920_mmu(struct target *target, int *enabled)
|
|
{
|
|
if (target->state != TARGET_HALTED) {
|
|
LOG_ERROR("%s: target not halted", __func__);
|
|
return ERROR_TARGET_INVALID;
|
|
}
|
|
|
|
*enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled;
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int arm920_virt2phys(struct target *target,
|
|
uint32_t virt, uint32_t *phys)
|
|
{
|
|
/** @todo Implement this! */
|
|
LOG_ERROR("%s: not implemented", __func__);
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
/** Reads a buffer, in the specified word size, with current MMU settings. */
|
|
int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
|
|
{
|
|
int retval;
|
|
|
|
retval = arm7_9_read_memory(target, address, size, count, buffer);
|
|
|
|
return retval;
|
|
}
|
|
|
|
|
|
static int arm920t_read_phys_memory(struct target *target,
|
|
uint32_t address, uint32_t size,
|
|
uint32_t count, uint8_t *buffer)
|
|
{
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
|
|
return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu,
|
|
address, size, count, buffer);
|
|
}
|
|
|
|
static int arm920t_write_phys_memory(struct target *target,
|
|
uint32_t address, uint32_t size,
|
|
uint32_t count, uint8_t *buffer)
|
|
{
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
|
|
return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
|
|
address, size, count, buffer);
|
|
}
|
|
|
|
|
|
/** Writes a buffer, in the specified word size, with current MMU settings. */
|
|
int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
|
|
{
|
|
int retval;
|
|
|
|
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
|
|
return retval;
|
|
|
|
/* This fn is used to write breakpoints, so we need to make sure
|
|
* that the data cache is flushed and the instruction cache is
|
|
* invalidated
|
|
*/
|
|
if (((size == 4) || (size == 2)) && (count == 1))
|
|
{
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
|
|
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
|
|
{
|
|
LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
|
|
/* MCR p15,0,Rd,c7,c10,2 */
|
|
retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
}
|
|
|
|
if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
|
|
{
|
|
LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
|
|
retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
}
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
// EXPORTED to FA256
|
|
int arm920t_soft_reset_halt(struct target *target)
|
|
{
|
|
int retval = ERROR_OK;
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm *armv4_5 = &arm7_9->armv4_5_common;
|
|
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
|
|
|
|
if ((retval = target_halt(target)) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
long long then = timeval_ms();
|
|
int timeout;
|
|
while (!(timeout = ((timeval_ms()-then) > 1000)))
|
|
{
|
|
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
|
|
{
|
|
embeddedice_read_reg(dbg_stat);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
} else
|
|
{
|
|
break;
|
|
}
|
|
if (debug_level >= 3)
|
|
{
|
|
/* do not eat all CPU, time out after 1 se*/
|
|
alive_sleep(100);
|
|
} else
|
|
{
|
|
keep_alive();
|
|
}
|
|
}
|
|
if (timeout)
|
|
{
|
|
LOG_ERROR("Failed to halt CPU after 1 sec");
|
|
return ERROR_TARGET_TIMEOUT;
|
|
}
|
|
|
|
target->state = TARGET_HALTED;
|
|
|
|
/* SVC, ARM state, IRQ and FIQ disabled */
|
|
uint32_t cpsr;
|
|
|
|
cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
|
|
cpsr &= ~0xff;
|
|
cpsr |= 0xd3;
|
|
arm_set_cpsr(armv4_5, cpsr);
|
|
armv4_5->cpsr->dirty = 1;
|
|
|
|
/* start fetching from 0x0 */
|
|
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
|
|
armv4_5->core_cache->reg_list[15].dirty = 1;
|
|
armv4_5->core_cache->reg_list[15].valid = 1;
|
|
|
|
arm920t_disable_mmu_caches(target, 1, 1, 1);
|
|
arm920t->armv4_5_mmu.mmu_enabled = 0;
|
|
arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
|
|
arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
|
|
|
|
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/* FIXME remove forward decls */
|
|
static int arm920t_mrc(struct target *target, int cpnum,
|
|
uint32_t op1, uint32_t op2,
|
|
uint32_t CRn, uint32_t CRm,
|
|
uint32_t *value);
|
|
static int arm920t_mcr(struct target *target, int cpnum,
|
|
uint32_t op1, uint32_t op2,
|
|
uint32_t CRn, uint32_t CRm,
|
|
uint32_t value);
|
|
|
|
int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
|
|
{
|
|
struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
|
|
|
|
arm7_9->armv4_5_common.mrc = arm920t_mrc;
|
|
arm7_9->armv4_5_common.mcr = arm920t_mcr;
|
|
|
|
/* initialize arm7/arm9 specific info (including armv4_5) */
|
|
arm9tdmi_init_arch_info(target, arm7_9, tap);
|
|
|
|
arm920t->common_magic = ARM920T_COMMON_MAGIC;
|
|
|
|
arm7_9->post_debug_entry = arm920t_post_debug_entry;
|
|
arm7_9->pre_restore_context = arm920t_pre_restore_context;
|
|
|
|
arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
|
|
arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
|
|
arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
|
|
arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
|
|
arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
|
|
arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
|
|
arm920t->armv4_5_mmu.has_tiny_pages = 1;
|
|
arm920t->armv4_5_mmu.mmu_enabled = 0;
|
|
|
|
/* disabling linefills leads to lockups, so keep them enabled for now
|
|
* this doesn't affect correctness, but might affect timing issues, if
|
|
* important data is evicted from the cache during the debug session
|
|
* */
|
|
arm920t->preserve_cache = 0;
|
|
|
|
/* override hw single-step capability from ARM9TDMI */
|
|
arm7_9->has_single_step = 1;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int arm920t_target_create(struct target *target, Jim_Interp *interp)
|
|
{
|
|
struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
|
|
|
|
return arm920t_init_arch_info(target, arm920t, target->tap);
|
|
}
|
|
|
|
COMMAND_HANDLER(arm920t_handle_read_cache_command)
|
|
{
|
|
int retval = ERROR_OK;
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm *armv4_5 = &arm7_9->armv4_5_common;
|
|
uint32_t cp15c15;
|
|
uint32_t cp15_ctrl, cp15_ctrl_saved;
|
|
uint32_t regs[16];
|
|
uint32_t *regs_p[16];
|
|
uint32_t C15_C_D_Ind, C15_C_I_Ind;
|
|
int i;
|
|
FILE *output;
|
|
struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
|
|
int segment, index;
|
|
struct reg *r;
|
|
|
|
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
if (CMD_ARGC != 1)
|
|
{
|
|
command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
|
|
{
|
|
LOG_DEBUG("error opening cache content file");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
for (i = 0; i < 16; i++)
|
|
regs_p[i] = ®s[i];
|
|
|
|
/* disable MMU and Caches */
|
|
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
cp15_ctrl_saved = cp15_ctrl;
|
|
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
|
|
|
|
/* read CP15 test state register */
|
|
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
|
|
jtag_execute_queue();
|
|
|
|
/* read DCache content */
|
|
fprintf(output, "DCache:\n");
|
|
|
|
/* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
|
|
for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
|
|
{
|
|
fprintf(output, "\nsegment: %i\n----------", segment);
|
|
|
|
/* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
|
|
regs[0] = 0x0 | (segment << 5);
|
|
arm9tdmi_write_core_regs(target, 0x1, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* D CAM Read, loads current victim into C15.C.D.Ind */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
|
|
|
|
/* read current victim */
|
|
arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
for (index = 0; index < 64; index++)
|
|
{
|
|
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
|
|
regs[0] = 0x0 | (segment << 5) | (index << 26);
|
|
arm9tdmi_write_core_regs(target, 0x1, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write DCache victim */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
|
|
|
|
/* Read D RAM */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
|
|
|
|
/* Read D CAM */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read D RAM and CAM content */
|
|
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
d_cache[segment][index].cam = regs[9];
|
|
|
|
/* mask LFSR[6] */
|
|
regs[9] &= 0xfffffffe;
|
|
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
|
|
|
|
for (i = 1; i < 9; i++)
|
|
{
|
|
d_cache[segment][index].data[i] = regs[i];
|
|
fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
|
|
}
|
|
|
|
}
|
|
|
|
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
|
|
regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
|
|
arm9tdmi_write_core_regs(target, 0x1, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write DCache victim */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
}
|
|
|
|
/* read ICache content */
|
|
fprintf(output, "ICache:\n");
|
|
|
|
/* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
|
|
for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
|
|
{
|
|
fprintf(output, "segment: %i\n----------", segment);
|
|
|
|
/* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
|
|
regs[0] = 0x0 | (segment << 5);
|
|
arm9tdmi_write_core_regs(target, 0x1, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* I CAM Read, loads current victim into C15.C.I.Ind */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
|
|
|
|
/* read current victim */
|
|
arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
for (index = 0; index < 64; index++)
|
|
{
|
|
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
|
|
regs[0] = 0x0 | (segment << 5) | (index << 26);
|
|
arm9tdmi_write_core_regs(target, 0x1, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write ICache victim */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
|
|
|
|
/* Read I RAM */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
|
|
|
|
/* Read I CAM */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read I RAM and CAM content */
|
|
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
i_cache[segment][index].cam = regs[9];
|
|
|
|
/* mask LFSR[6] */
|
|
regs[9] &= 0xfffffffe;
|
|
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
|
|
|
|
for (i = 1; i < 9; i++)
|
|
{
|
|
i_cache[segment][index].data[i] = regs[i];
|
|
fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
|
|
}
|
|
}
|
|
|
|
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
|
|
regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
|
|
arm9tdmi_write_core_regs(target, 0x1, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write ICache victim */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
}
|
|
|
|
/* restore CP15 MMU and Cache settings */
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
|
|
|
|
command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
|
|
|
|
fclose(output);
|
|
|
|
if (!is_arm_mode(armv4_5->core_mode))
|
|
return ERROR_FAIL;
|
|
|
|
/* force writeback of the valid data */
|
|
r = armv4_5->core_cache->reg_list;
|
|
r[0].dirty = r[0].valid;
|
|
r[1].dirty = r[1].valid;
|
|
r[2].dirty = r[2].valid;
|
|
r[3].dirty = r[3].valid;
|
|
r[4].dirty = r[4].valid;
|
|
r[5].dirty = r[5].valid;
|
|
r[6].dirty = r[6].valid;
|
|
r[7].dirty = r[7].valid;
|
|
|
|
r = arm_reg_current(armv4_5, 8);
|
|
r->dirty = r->valid;
|
|
|
|
r = arm_reg_current(armv4_5, 9);
|
|
r->dirty = r->valid;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(arm920t_handle_read_mmu_command)
|
|
{
|
|
int retval = ERROR_OK;
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm *armv4_5 = &arm7_9->armv4_5_common;
|
|
uint32_t cp15c15;
|
|
uint32_t cp15_ctrl, cp15_ctrl_saved;
|
|
uint32_t regs[16];
|
|
uint32_t *regs_p[16];
|
|
int i;
|
|
FILE *output;
|
|
uint32_t Dlockdown, Ilockdown;
|
|
struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
|
|
int victim;
|
|
struct reg *r;
|
|
|
|
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
if (CMD_ARGC != 1)
|
|
{
|
|
command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
|
|
{
|
|
LOG_DEBUG("error opening mmu content file");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
for (i = 0; i < 16; i++)
|
|
regs_p[i] = ®s[i];
|
|
|
|
/* disable MMU and Caches */
|
|
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
cp15_ctrl_saved = cp15_ctrl;
|
|
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
|
|
|
|
/* read CP15 test state register */
|
|
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
/* prepare reading D TLB content
|
|
* */
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Read D TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read D TLB lockdown stored to r1 */
|
|
arm9tdmi_read_core_regs(target, 0x2, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
Dlockdown = regs[1];
|
|
|
|
for (victim = 0; victim < 64; victim += 8)
|
|
{
|
|
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
|
|
* base remains unchanged, victim goes through entries 0 to 63 */
|
|
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
|
|
arm9tdmi_write_core_regs(target, 0x2, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write D TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
|
|
|
|
/* Read D TLB CAM */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read D TLB CAM content stored to r2-r9 */
|
|
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
for (i = 0; i < 8; i++)
|
|
d_tlb[victim + i].cam = regs[i + 2];
|
|
}
|
|
|
|
for (victim = 0; victim < 64; victim++)
|
|
{
|
|
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
|
|
* base remains unchanged, victim goes through entries 0 to 63 */
|
|
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
|
|
arm9tdmi_write_core_regs(target, 0x2, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write D TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
|
|
|
|
/* Read D TLB RAM1 */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
|
|
|
|
/* Read D TLB RAM2 */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read D TLB RAM content stored to r2 and r3 */
|
|
arm9tdmi_read_core_regs(target, 0xc, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
d_tlb[victim].ram1 = regs[2];
|
|
d_tlb[victim].ram2 = regs[3];
|
|
}
|
|
|
|
/* restore D TLB lockdown */
|
|
regs[1] = Dlockdown;
|
|
arm9tdmi_write_core_regs(target, 0x2, regs);
|
|
|
|
/* Write D TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
|
|
|
|
/* prepare reading I TLB content
|
|
* */
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Read I TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read I TLB lockdown stored to r1 */
|
|
arm9tdmi_read_core_regs(target, 0x2, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
Ilockdown = regs[1];
|
|
|
|
for (victim = 0; victim < 64; victim += 8)
|
|
{
|
|
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
|
|
* base remains unchanged, victim goes through entries 0 to 63 */
|
|
regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
|
|
arm9tdmi_write_core_regs(target, 0x2, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write I TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
|
|
|
|
/* Read I TLB CAM */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read I TLB CAM content stored to r2-r9 */
|
|
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
for (i = 0; i < 8; i++)
|
|
i_tlb[i + victim].cam = regs[i + 2];
|
|
}
|
|
|
|
for (victim = 0; victim < 64; victim++)
|
|
{
|
|
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
|
|
* base remains unchanged, victim goes through entries 0 to 63 */
|
|
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
|
|
arm9tdmi_write_core_regs(target, 0x2, regs);
|
|
|
|
/* set interpret mode */
|
|
cp15c15 |= 0x1;
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
|
|
|
|
/* Write I TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
|
|
|
|
/* Read I TLB RAM1 */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
|
|
|
|
/* Read I TLB RAM2 */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
|
|
|
|
/* clear interpret mode */
|
|
cp15c15 &= ~0x1;
|
|
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
|
|
|
|
/* read I TLB RAM content stored to r2 and r3 */
|
|
arm9tdmi_read_core_regs(target, 0xc, regs_p);
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
i_tlb[victim].ram1 = regs[2];
|
|
i_tlb[victim].ram2 = regs[3];
|
|
}
|
|
|
|
/* restore I TLB lockdown */
|
|
regs[1] = Ilockdown;
|
|
arm9tdmi_write_core_regs(target, 0x2, regs);
|
|
|
|
/* Write I TLB lockdown */
|
|
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
|
|
|
|
/* restore CP15 MMU and Cache settings */
|
|
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
|
|
|
|
/* output data to file */
|
|
fprintf(output, "D TLB content:\n");
|
|
for (i = 0; i < 64; i++)
|
|
{
|
|
fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
|
|
}
|
|
|
|
fprintf(output, "\n\nI TLB content:\n");
|
|
for (i = 0; i < 64; i++)
|
|
{
|
|
fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
|
|
}
|
|
|
|
command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
|
|
|
|
fclose(output);
|
|
|
|
if (!is_arm_mode(armv4_5->core_mode))
|
|
return ERROR_FAIL;
|
|
|
|
/* force writeback of the valid data */
|
|
r = armv4_5->core_cache->reg_list;
|
|
r[0].dirty = r[0].valid;
|
|
r[1].dirty = r[1].valid;
|
|
r[2].dirty = r[2].valid;
|
|
r[3].dirty = r[3].valid;
|
|
r[4].dirty = r[4].valid;
|
|
r[5].dirty = r[5].valid;
|
|
r[6].dirty = r[6].valid;
|
|
r[7].dirty = r[7].valid;
|
|
|
|
r = arm_reg_current(armv4_5, 8);
|
|
r->dirty = r->valid;
|
|
|
|
r = arm_reg_current(armv4_5, 9);
|
|
r->dirty = r->valid;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(arm920t_handle_cp15_command)
|
|
{
|
|
int retval;
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
|
|
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/* one or more argument, access a single register (write if second argument is given */
|
|
if (CMD_ARGC >= 1)
|
|
{
|
|
int address;
|
|
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
|
|
|
|
if (CMD_ARGC == 1)
|
|
{
|
|
uint32_t value;
|
|
if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "couldn't access reg %i", address);
|
|
return ERROR_OK;
|
|
}
|
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
|
|
command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
|
|
}
|
|
else if (CMD_ARGC == 2)
|
|
{
|
|
uint32_t value;
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
|
|
if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "couldn't access reg %i", address);
|
|
return ERROR_OK;
|
|
}
|
|
command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
|
|
}
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(arm920t_handle_cp15i_command)
|
|
{
|
|
int retval;
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
|
|
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/* one or more argument, access a single register (write if second argument is given */
|
|
if (CMD_ARGC >= 1)
|
|
{
|
|
uint32_t opcode;
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
|
|
|
|
if (CMD_ARGC == 1)
|
|
{
|
|
uint32_t value;
|
|
if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
|
|
return ERROR_OK;
|
|
}
|
|
|
|
command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
|
|
}
|
|
else if (CMD_ARGC == 2)
|
|
{
|
|
uint32_t value;
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
|
|
if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
|
|
return ERROR_OK;
|
|
}
|
|
command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
|
|
}
|
|
else if (CMD_ARGC == 3)
|
|
{
|
|
uint32_t value;
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
|
|
uint32_t address;
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
|
|
if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
|
|
return ERROR_OK;
|
|
}
|
|
command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(arm920t_handle_cache_info_command)
|
|
{
|
|
int retval;
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct arm920t_common *arm920t = target_to_arm920(target);
|
|
|
|
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
|
|
}
|
|
|
|
|
|
static int arm920t_mrc(struct target *target, int cpnum,
|
|
uint32_t op1, uint32_t op2,
|
|
uint32_t CRn, uint32_t CRm,
|
|
uint32_t *value)
|
|
{
|
|
if (cpnum!=15)
|
|
{
|
|
LOG_ERROR("Only cp15 is supported");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
/* read "to" r0 */
|
|
return arm920t_read_cp15_interpreted(target,
|
|
ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
|
|
0, value);
|
|
}
|
|
|
|
static int arm920t_mcr(struct target *target, int cpnum,
|
|
uint32_t op1, uint32_t op2,
|
|
uint32_t CRn, uint32_t CRm,
|
|
uint32_t value)
|
|
{
|
|
if (cpnum!=15)
|
|
{
|
|
LOG_ERROR("Only cp15 is supported");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
/* write "from" r0 */
|
|
return arm920t_write_cp15_interpreted(target,
|
|
ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
|
|
0, value);
|
|
}
|
|
|
|
static const struct command_registration arm920t_exec_command_handlers[] = {
|
|
{
|
|
.name = "cp15",
|
|
.handler = arm920t_handle_cp15_command,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "display/modify cp15 register",
|
|
.usage = "regnum [value]",
|
|
},
|
|
{
|
|
.name = "cp15i",
|
|
.handler = arm920t_handle_cp15i_command,
|
|
.mode = COMMAND_EXEC,
|
|
/* prefer using less error-prone "arm mcr" or "arm mrc" */
|
|
.help = "display/modify cp15 register using ARM opcode"
|
|
" (DEPRECATED)",
|
|
.usage = "instruction [value [address]]",
|
|
},
|
|
{
|
|
.name = "cache_info",
|
|
.handler = arm920t_handle_cache_info_command,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "display information about target caches",
|
|
},
|
|
{
|
|
.name = "read_cache",
|
|
.handler = arm920t_handle_read_cache_command,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "dump I/D cache content to file",
|
|
.usage = "filename",
|
|
},
|
|
{
|
|
.name = "read_mmu",
|
|
.handler = arm920t_handle_read_mmu_command,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "dump I/D mmu content to file",
|
|
.usage = "filename",
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
const struct command_registration arm920t_command_handlers[] = {
|
|
{
|
|
.chain = arm9tdmi_command_handlers,
|
|
},
|
|
{
|
|
.name = "arm920t",
|
|
.mode = COMMAND_ANY,
|
|
.help = "arm920t command group",
|
|
.chain = arm920t_exec_command_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
/** Holds methods for ARM920 targets. */
|
|
struct target_type arm920t_target =
|
|
{
|
|
.name = "arm920t",
|
|
|
|
.poll = arm7_9_poll,
|
|
.arch_state = arm920t_arch_state,
|
|
|
|
.target_request_data = arm7_9_target_request_data,
|
|
|
|
.halt = arm7_9_halt,
|
|
.resume = arm7_9_resume,
|
|
.step = arm7_9_step,
|
|
|
|
.assert_reset = arm7_9_assert_reset,
|
|
.deassert_reset = arm7_9_deassert_reset,
|
|
.soft_reset_halt = arm920t_soft_reset_halt,
|
|
|
|
.get_gdb_reg_list = arm_get_gdb_reg_list,
|
|
|
|
.read_memory = arm920t_read_memory,
|
|
.write_memory = arm920t_write_memory,
|
|
.read_phys_memory = arm920t_read_phys_memory,
|
|
.write_phys_memory = arm920t_write_phys_memory,
|
|
.mmu = arm920_mmu,
|
|
.virt2phys = arm920_virt2phys,
|
|
|
|
.bulk_write_memory = arm7_9_bulk_write_memory,
|
|
|
|
.checksum_memory = arm_checksum_memory,
|
|
.blank_check_memory = arm_blank_check_memory,
|
|
|
|
.run_algorithm = armv4_5_run_algorithm,
|
|
|
|
.add_breakpoint = arm7_9_add_breakpoint,
|
|
.remove_breakpoint = arm7_9_remove_breakpoint,
|
|
.add_watchpoint = arm7_9_add_watchpoint,
|
|
.remove_watchpoint = arm7_9_remove_watchpoint,
|
|
|
|
.commands = arm920t_command_handlers,
|
|
.target_create = arm920t_target_create,
|
|
.init_target = arm9tdmi_init_target,
|
|
.examine = arm7_9_examine,
|
|
.check_reset = arm7_9_check_reset,
|
|
};
|