139 lines
3.0 KiB
C
139 lines
3.0 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARM_DISASSEMBLER_H
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#define ARM_DISASSEMBLER_H
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#include "types.h"
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enum arm_instruction_type
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{
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ARM_UNKNOWN_INSTUCTION,
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/* Branch instructions */
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ARM_B,
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ARM_BL,
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ARM_BX,
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ARM_BLX,
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/* Data processing instructions */
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ARM_AND,
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ARM_EOR,
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ARM_SUB,
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ARM_RSB,
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ARM_ADD,
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ARM_ADC,
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ARM_SBC,
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ARM_RSC,
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ARM_TST,
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ARM_TEQ,
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ARM_CMP,
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ARM_CMN,
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ARM_ORR,
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ARM_MOV,
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ARM_BIC,
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ARM_MVN,
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/* Load/store instructions */
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ARM_LDR,
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ARM_LDRB,
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ARM_LDRT,
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ARM_LDRBT,
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ARM_LDRH,
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ARM_LDRSB,
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ARM_LDRSH,
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ARM_LDM,
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ARM_STR,
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ARM_STRB,
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ARM_STRT,
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ARM_STRBT,
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ARM_STRH,
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ARM_STM,
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/* Status register access instructions */
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ARM_MRS,
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ARM_MSR,
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/* Multiply instructions */
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ARM_MUL,
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ARM_MLA,
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ARM_SMULL,
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ARM_SMLAL,
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ARM_UMULL,
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ARM_UMLAL,
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/* Miscellaneous instructions */
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ARM_CLZ,
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/* Exception generating instructions */
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ARM_BKPT,
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ARM_SWI,
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/* Coprocessor instructions */
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ARM_CDP,
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ARM_LDC,
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ARM_STC,
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ARM_MCR,
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ARM_MRC,
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/* Semaphore instructions */
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ARM_SWP,
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ARM_SWPB,
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/* Enhanced DSP extensions */
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ARM_MCRR,
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ARM_MRRC,
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ARM_PLD,
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ARM_QADD,
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ARM_QDADD,
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ARM_QSUB,
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ARM_QDSUB,
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ARM_SMLAxy,
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ARM_SMLALxy,
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ARM_SMLAWy,
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ARM_SMULxy,
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ARM_SMULWy,
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ARM_LDRD,
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ARM_STRD,
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ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
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};
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typedef struct arm_instruction_s
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{
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enum arm_instruction_type type;
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char text[128];
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u32 opcode;
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/* target */
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u32 target_address;
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} arm_instruction_t;
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extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
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#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])
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#endif /* ARM_DISASSEMBLER_H */
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