ba00ef3c40
- Moved variant-independent code to lpc17xx.cfg, which will be included from lpc17??.cfg files automatically. - lpc1768.cfg filled with variant-dependent code. Change-Id: I7dabe6ed7da7be640ed38c13aaaa096b8796d9a0 Signed-off-by: Vandra Akos <axos88@gmail.com> Reviewed-on: http://openocd.zylin.com/675 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
18 lines
637 B
INI
18 lines
637 B
INI
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
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set CHIPNAME lpc1768
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set CPUTAPID 0x4ba00477
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set CPURAMSIZE 0x8000
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set CPUROMSIZE 0x80000
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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set CCLK 4000
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#Include the main configuration file.
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source [find target/lpc17xx.cfg];
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