7c38f24529
The patch was created automatically using the following script: %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- (cat << EOF ftdi_device_desc ftdi device_desc ftdi_serial ftdi serial ftdi_channel ftdi channel ftdi_layout_init ftdi layout_init ftdi_layout_signal ftdi layout_signal ftdi_set_signal ftdi set_signal ftdi_get_signal ftdi get_signal ftdi_vid_pid ftdi vid_pid ftdi_tdo_sample_edge ftdi tdo_sample_edge EOF ) | while read a b; do sed -i "s/$a/$b/g" $(find tcl -type f -name "*.cfg" ) done %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: Iff781f37bb5511b7e15cbe6dcdf6d28e89fb174f Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6333 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
37 lines
1.2 KiB
INI
37 lines
1.2 KiB
INI
#
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# Numato Mimas A7 - Artix 7 FPGA Board
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#
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# https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet
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#
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# Note: Connect external DC power supply if programming a heavy design onto FPGA.
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# Programming while powering via USB may lead to programming failure.
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# Therefore, prefer external power supply.
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adapter driver ftdi
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ftdi device_desc "Mimas Artix 7 FPGA Module"
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ftdi vid_pid 0x2a19 0x1009
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# channel 0 is for custom purpose by users (like uart, fifo etc)
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# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers)
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ftdi channel 1
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ftdi tdo_sample_edge falling
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# FTDI Pin Layout
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#
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# +--------+-------+-------+-------+-------+-------+-------+-------+
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# | DBUS7 | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 |
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# +--------+-------+-------+-------+-------+-------+-------+-------+
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# | PROG_B | OE_N | NC | NC | TMS | TDO | TDI | TCK |
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# +--------+-------+-------+-------+-------+-------+-------+-------+
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#
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# OE_N is JTAG buffer output enable signal (active-low)
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# PROG_B is not used, so left as input to FTDI.
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#
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ftdi layout_init 0x0008 0x004b
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reset_config none
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adapter speed 30000
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source [find cpld/xilinx-xc7.cfg]
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source [find cpld/jtagspi.cfg]
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