ba71e8c521
for - pio - pmc - rstc - wdt - sdramc - smc Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
30 lines
1.3 KiB
INI
30 lines
1.3 KiB
INI
set PIO_PER 0x00 ;# Enable Register
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set PIO_PDR 0x04 ;# Disable Register
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set PIO_PSR 0x08 ;# Status Register
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set PIO_OER 0x10 ;# Output Enable Register
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set PIO_ODR 0x14 ;# Output Disable Register
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set PIO_OSR 0x18 ;# Output Status Register
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set PIO_IFER 0x20 ;# Glitch Input Filter Enable
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set PIO_IFDR 0x24 ;# Glitch Input Filter Disable
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set PIO_IFSR 0x28 ;# Glitch Input Filter Status
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set PIO_SODR 0x30 ;# Set Output Data Register
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set PIO_CODR 0x34 ;# Clear Output Data Register
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set PIO_ODSR 0x38 ;# Output Data Status Register
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set PIO_PDSR 0x3c ;# Pin Data Status Register
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set PIO_IER 0x40 ;# Interrupt Enable Register
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set PIO_IDR 0x44 ;# Interrupt Disable Register
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set PIO_IMR 0x48 ;# Interrupt Mask Register
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set PIO_ISR 0x4c ;# Interrupt Status Register
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set PIO_MDER 0x50 ;# Multi-driver Enable Register
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set PIO_MDDR 0x54 ;# Multi-driver Disable Register
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set PIO_MDSR 0x58 ;# Multi-driver Status Register
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set PIO_PUDR 0x60 ;# Pull-up Disable Register
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set PIO_PUER 0x64 ;# Pull-up Enable Register
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set PIO_PUSR 0x68 ;# Pull-up Status Register
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set PIO_ASR 0x70 ;# Peripheral A Select Register
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set PIO_BSR 0x74 ;# Peripheral B Select Register
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set PIO_ABSR 0x78 ;# AB Status Register
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set PIO_OWER 0xa0 ;# Output Write Enable Register
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set PIO_OWDR 0xa4 ;# Output Write Disable Register
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set PIO_OWSR 0xa8 ;# Output Write Status Register
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