f998a2aaf1
Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6097 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
38 lines
1.0 KiB
INI
38 lines
1.0 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Cadence virtual debug interface
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# Arm v8 64b Cortex A
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if {![info exists _CORES]} {
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set _CORES 1
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}
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if {![info exists _CHIPNAME]} {
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set _CHIPNAME aarch64
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}
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set _TARGETNAME $_CHIPNAME.cpu
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set _CTINAME $_CHIPNAME.cti
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set DBGBASE {0x80810000 0x80910000}
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set CTIBASE {0x80820000 0x80920000}
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dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
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$_CHIPNAME.dap apsel 1
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for { set _core 0 } { $_core < $_CORES } { incr _core } \
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{
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cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]
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set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
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-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
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if { $_core != 0 } {
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# non-boot core examination may fail
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set _command "$_command -defer-examine"
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set _smp_command "$_smp_command $_TARGETNAME.$_core"
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} else {
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set _smp_command "target smp $_TARGETNAME.$_core"
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}
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eval $_command
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}
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eval $_smp_command
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# default target is core 0
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targets $_TARGETNAME.0
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