openocd/tcl/board/arm_musca_a.cfg
Antonio Borneo 38ac08c1c2 tcl: replace the deprecated commands with "adapter ..."
Avoid annoying "deprecated" messages while running the scripts
distributed with OpenOCD code.
Change automatically created with commands
	sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f)
	sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f)
	sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f)

Minor indentation issue fixed manually in
	tcl/board/at91sam9g20-ek.cfg
	tcl/target/at91sam9260_ext_RAM_ext_flash.cfg

Change-Id: I425fd56c0c88cd6b06124621306eeb89166dfe71
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5284
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-01-29 06:34:43 +00:00

45 lines
1.3 KiB
INI

#
# Configuration script for ARM Musca-A development board
#
# For now we do not support Musca A flash programming using OpenOCD. However, a
# work area is configured for flash programming speed up.
#
# GDB considers all memory as RAM unless target supplies a memory map.
# OpenOCD will only send memory map if flash banks are configured. Otherwise,
# configure GDB after connection by issuing following commands:
# (gdb) mem 0x10200000 0x109FFFFF ro
# (gdb) mem 0x00200000 0x009FFFFF ro
# (gdb) set mem inaccessible-by-default off
# ARM Musca A board supports both JTAG and SWD transports.
source [find target/swj-dp.tcl]
# set a safe JTAG clock speed, can be overridden
adapter speed 1000
global _CHIPNAME
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME MUSCA_A
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x6ba00477
}
# Enable CPU1 debugging as a separate GDB target
set _ENABLE_CPU1 1
# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU
set WORKAREASIZE_CPU0 0x2000
set WORKAREASIZE_CPU1 0x2000
# Set SRAM bank 1 to be used for work area. Override here if needed.
set WORKAREAADDR_CPU0 0x30008000
set WORKAREAADDR_CPU1 0x3000A000
source [find target/arm_corelink_sse200.cfg]