8f777bc1a6
Currently it is impossible to flash ELF with correct offsets. The reason is a bogus offset calculation extracted from base. Since any other spi drivers do not care about base, do the same for ath79 as well. Change-Id: I9e46e01c9e7a709c2d07da9203c634f302603afd Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4821 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
33 lines
915 B
INI
33 lines
915 B
INI
# Product page:
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# https://www.dptechnics.com/en/products/dpt-board-v1.html
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#
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# JTAG is a 5 pin array located close to main module in following order:
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# 1. JTAG TCK
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# 2. JTAG TDO
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# 3. JTAG TDI
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# 4. JTAG TMS
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# 5. GND The GND is located near letter G of word JTAG on board.
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#
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# Two RST pins are connected to:
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# 1. GND
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# 2. GPIO11 this pin is located near letter R of word RST.
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#
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# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
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# with 10K resistor connected to V3.3 pin.
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#
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# This board is powered from micro USB connector. No real reset pin or button, for
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# example RESET_L is available.
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source [find target/atheros_ar9331.cfg]
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$_TARGETNAME configure -event reset-init {
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ar9331_25mhz_pll_init
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sleep 1
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ar9331_ddr2_init
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}
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set ram_boot_address 0xa0000000
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$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
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flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
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