03e9729043
all other at91 cfg files already has this fix. It also fix "No flash at address 0x...." error when JTAG chain consist of more than one at91sam7sx cores during attempt to flash other than first mcu in chain. Change-Id: I7785d9103d0fc494b6a823e2c73f850373ffe112 Signed-off-by: Sergey A. Borshch <sb-sf@users.sourceforge.net> Reviewed-on: http://openocd.zylin.com/1812 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
54 lines
1.5 KiB
INI
54 lines
1.5 KiB
INI
#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config srst_only srst_pulls_trst
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91sam7s
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x3f0f0f0f
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
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$_TARGETNAME configure -event reset-init {
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soft_reset_halt
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# RSTC_CR : Reset peripherals
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mww 0xfffffd00 0xa5000004
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# disable watchdog
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mww 0xfffffd44 0x00008000
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# enable user reset
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mww 0xfffffd08 0xa5000001
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# CKGR_MOR : enable the main oscillator
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mww 0xfffffc20 0x00000601
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sleep 10
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# CKGR_PLLR: 96.1097 MHz
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mww 0xfffffc2c 0x00481c0e
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sleep 10
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# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
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mww 0xfffffc30 0x00000007
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sleep 10
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# MC_FMR: flash mode (FWS=1,FMCN=73)
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mww 0xffffff60 0x00490100
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sleep 100
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}
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$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
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#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
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