478 lines
16 KiB
C
478 lines
16 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARM_ADI_V5_H
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#define ARM_ADI_V5_H
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/**
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* @file
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* This defines formats and data structures used to talk to ADIv5 entities.
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* Those include a DAP, different types of Debug Port (DP), and memory mapped
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* resources accessed through a MEM-AP.
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*/
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#include "arm_jtag.h"
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/* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
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* is no longer JTAG-specific
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*/
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#define JTAG_DP_DPACC 0xA
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#define JTAG_DP_APACC 0xB
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/* three-bit ACK values for SWD access (sent LSB first) */
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#define SWD_ACK_OK 0x4
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#define SWD_ACK_WAIT 0x2
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#define SWD_ACK_FAULT 0x1
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#define DPAP_WRITE 0
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#define DPAP_READ 1
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/* A[3:0] for DP registers; A[1:0] are always zero.
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* - JTAG accesses all of these via JTAG_DP_DPACC, except for
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* IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
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* - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
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*/
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#define DP_IDCODE 0 /* SWD: read */
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#define DP_ABORT 0 /* SWD: write */
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#define DP_CTRL_STAT 0x4 /* r/w */
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#define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
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#define DP_RESEND 0x8 /* SWD: read */
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#define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
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#define DP_RDBUFF 0xC /* read-only */
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#define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8)) /* 1..4 clocks */
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#define WCR_TO_PRESCALE(wcr) (7 & ((wcr))) /* impl defined */
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/* Fields of the DP's AP ABORT register */
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#define DAPABORT (1 << 0)
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#define STKCMPCLR (1 << 1) /* SWD-only */
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#define STKERRCLR (1 << 2) /* SWD-only */
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#define WDERRCLR (1 << 3) /* SWD-only */
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#define ORUNERRCLR (1 << 4) /* SWD-only */
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/* Fields of the DP's CTRL/STAT register */
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#define CORUNDETECT (1 << 0)
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#define SSTICKYORUN (1 << 1)
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/* 3:2 - transaction mode (e.g. pushed compare) */
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#define SSTICKYCMP (1 << 4)
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#define SSTICKYERR (1 << 5)
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#define READOK (1 << 6) /* SWD-only */
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#define WDATAERR (1 << 7) /* SWD-only */
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/* 11:8 - mask lanes for pushed compare or verify ops */
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/* 21:12 - transaction counter */
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#define CDBGRSTREQ (1 << 26)
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#define CDBGRSTACK (1 << 27)
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#define CDBGPWRUPREQ (1 << 28)
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#define CDBGPWRUPACK (1 << 29)
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#define CSYSPWRUPREQ (1 << 30)
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#define CSYSPWRUPACK (1 << 31)
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/* MEM-AP register addresses */
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/* TODO: rename as MEM_AP_REG_* */
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#define AP_REG_CSW 0x00
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#define AP_REG_TAR 0x04
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#define AP_REG_DRW 0x0C
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#define AP_REG_BD0 0x10
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#define AP_REG_BD1 0x14
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#define AP_REG_BD2 0x18
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#define AP_REG_BD3 0x1C
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#define AP_REG_CFG 0xF4 /* big endian? */
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#define AP_REG_BASE 0xF8
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/* Generic AP register address */
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#define AP_REG_IDR 0xFC
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/* Fields of the MEM-AP's CSW register */
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#define CSW_8BIT 0
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#define CSW_16BIT 1
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#define CSW_32BIT 2
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#define CSW_ADDRINC_MASK (3 << 4)
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#define CSW_ADDRINC_OFF 0
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#define CSW_ADDRINC_SINGLE (1 << 4)
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#define CSW_ADDRINC_PACKED (2 << 4)
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#define CSW_DEVICE_EN (1 << 6)
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#define CSW_TRIN_PROG (1 << 7)
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#define CSW_SPIDEN (1 << 23)
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/* 30:24 - implementation-defined! */
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#define CSW_HPROT (1 << 25) /* ? */
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#define CSW_MASTER_DEBUG (1 << 29) /* ? */
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#define CSW_SPROT (1 << 30)
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#define CSW_DBGSWENABLE (1 << 31)
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/**
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* This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
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* A DAP has two types of component: one Debug Port (DP), which is a
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* transport agent; and at least one Access Port (AP), controlling
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* resource access. Most common is a MEM-AP, for memory access.
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*
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* There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
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* Accordingly, this interface is responsible for hiding the transport
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* differences so upper layer code can largely ignore them.
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*
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* When the chip is implemented with JTAG-DP or SW-DP, the transport is
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* fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
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* a choice made at board design time (by only using the SWD pins), or
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* as part of setting up a debug session (if all the dual-role JTAG/SWD
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* signals are available).
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*/
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struct adiv5_dap {
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const struct dap_ops *ops;
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struct arm_jtag *jtag_info;
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/* Control config */
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uint32_t dp_ctrl_stat;
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uint32_t apcsw[256];
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uint32_t apsel;
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/**
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* Cache for DP_SELECT bits identifying the current AP. A DAP may
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* connect to multiple APs, such as one MEM-AP for general access,
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* another reserved for accessing debug modules, and a JTAG-DP.
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* "-1" indicates no cached value.
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*/
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uint32_t ap_current;
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/**
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* Cache for DP_SELECT bits identifying the current four-word AP
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* register bank. This caches AP register addresss bits 7:4; JTAG
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* and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
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* "-1" indicates no cached value.
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*/
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uint32_t ap_bank_value;
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/**
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* Cache for (MEM-AP) AP_REG_CSW register value. This is written to
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* configure an access mode, such as autoincrementing AP_REG_TAR during
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* word access. "-1" indicates no cached value.
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*/
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uint32_t ap_csw_value;
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/**
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* Cache for (MEM-AP) AP_REG_TAR register value This is written to
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* configure the address being read or written
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* "-1" indicates no cached value.
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*/
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uint32_t ap_tar_value;
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/* information about current pending SWjDP-AHBAP transaction */
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uint8_t ack;
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/**
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* Configures how many extra tck clocks are added after starting a
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* MEM-AP access before we try to read its status (and/or result).
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*/
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uint32_t memaccess_tck;
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/* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
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uint32_t tar_autoincr_block;
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};
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/**
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* Transport-neutral representation of queued DAP transactions, supporting
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* both JTAG and SWD transports. All submitted transactions are logically
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* queued, until the queue is executed by run(). Some implementations might
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* execute transactions as soon as they're submitted, but no status is made
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* availablue until run().
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*/
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struct dap_ops {
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/** If the DAP transport isn't SWD, it must be JTAG. Upper level
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* code may need to care about the difference in some cases.
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*/
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bool is_swd;
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/** Reads the DAP's IDCODe register. */
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int (*queue_idcode_read)(struct adiv5_dap *dap,
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uint8_t *ack, uint32_t *data);
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/** DP register read. */
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int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
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uint32_t *data);
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/** DP register write. */
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int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
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uint32_t data);
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/** AP register read. */
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int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
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uint32_t *data);
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/** AP register write. */
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int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
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uint32_t data);
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/** AP read block. */
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int (*queue_ap_read_block)(struct adiv5_dap *dap, unsigned reg,
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uint32_t blocksize, uint8_t *buffer);
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/** AP operation abort. */
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int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
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/** Executes all queued DAP operations. */
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int (*run)(struct adiv5_dap *dap);
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};
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/*
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* Access Port types
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*/
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enum ap_type {
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AP_TYPE_AHB_AP = 0x01, /* AHB Memory-AP */
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AP_TYPE_APB_AP = 0x02, /* APB Memory-AP */
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AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
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};
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/**
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* Queue an IDCODE register read. This is primarily useful for SWD
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* transports, where it is required as part of link initialization.
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* (For JTAG, this register is read as part of scan chain setup.)
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*
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* @param dap The DAP used for reading.
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* @param ack Pointer to where transaction status will be stored.
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* @param data Pointer saying where to store the IDCODE value.
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
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uint8_t *ack, uint32_t *data)
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{
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assert(dap->ops != NULL);
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return dap->ops->queue_idcode_read(dap, ack, data);
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}
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/**
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* Queue a DP register read.
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* Note that not all DP registers are readable; also, that JTAG and SWD
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* have slight differences in DP register support.
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*
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* @param dap The DAP used for reading.
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* @param reg The two-bit number of the DP register being read.
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* @param data Pointer saying where to store the register's value
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* (in host endianness).
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_queue_dp_read(struct adiv5_dap *dap,
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unsigned reg, uint32_t *data)
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{
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assert(dap->ops != NULL);
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return dap->ops->queue_dp_read(dap, reg, data);
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}
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/**
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* Queue a DP register write.
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* Note that not all DP registers are writable; also, that JTAG and SWD
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* have slight differences in DP register support.
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*
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* @param dap The DAP used for writing.
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* @param reg The two-bit number of the DP register being written.
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* @param data Value being written (host endianness)
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_queue_dp_write(struct adiv5_dap *dap,
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unsigned reg, uint32_t data)
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{
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assert(dap->ops != NULL);
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return dap->ops->queue_dp_write(dap, reg, data);
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}
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/**
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* Queue an AP register read.
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*
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* @param dap The DAP used for reading.
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* @param reg The number of the AP register being read.
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* @param data Pointer saying where to store the register's value
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* (in host endianness).
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_queue_ap_read(struct adiv5_dap *dap,
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unsigned reg, uint32_t *data)
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{
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assert(dap->ops != NULL);
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return dap->ops->queue_ap_read(dap, reg, data);
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}
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/**
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* Queue an AP register write.
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*
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* @param dap The DAP used for writing.
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* @param reg The number of the AP register being written.
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* @param data Value being written (host endianness)
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_queue_ap_write(struct adiv5_dap *dap,
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unsigned reg, uint32_t data)
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{
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assert(dap->ops != NULL);
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return dap->ops->queue_ap_write(dap, reg, data);
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}
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/**
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* Queue an AP block read.
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*
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* @param dap The DAP used for reading.
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* @param reg The number of the AP register being read.
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* @param blocksize The number of the AP register being read.
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* @param buffer Pointer saying where to store the data
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* (in host endianness).
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_queue_ap_read_block(struct adiv5_dap *dap,
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unsigned reg, unsigned blocksize, uint8_t *buffer)
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{
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assert(dap->ops != NULL);
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return dap->ops->queue_ap_read_block(dap, reg, blocksize, buffer);
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}
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/**
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* Queue an AP abort operation. The current AP transaction is aborted,
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* including any update of the transaction counter. The AP is left in
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* an unknown state (so it must be re-initialized). For use only after
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* the AP has reported WAIT status for an extended period.
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*
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* @param dap The DAP used for writing.
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* @param ack Pointer to where transaction status will be stored.
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
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{
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assert(dap->ops != NULL);
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return dap->ops->queue_ap_abort(dap, ack);
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}
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/**
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* Perform all queued DAP operations, and clear any errors posted in the
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* CTRL_STAT register when they are done. Note that if more than one AP
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* operation will be queued, one of the first operations in the queue
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* should probably enable CORUNDETECT in the CTRL/STAT register.
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*
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* @param dap The DAP used.
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*
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* @return ERROR_OK for success, else a fault code.
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*/
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static inline int dap_run(struct adiv5_dap *dap)
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{
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assert(dap->ops != NULL);
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return dap->ops->run(dap);
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}
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/** Accessor for currently selected DAP-AP number (0..255) */
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static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
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{
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return (uint8_t)(swjdp->ap_current >> 24);
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}
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/* AP selection applies to future AP transactions */
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void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
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/* Queued AP transactions */
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int dap_setup_accessport(struct adiv5_dap *swjdp,
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uint32_t csw, uint32_t tar);
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/* Queued MEM-AP memory mapped single word transfers */
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int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
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int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
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/* Synchronous MEM-AP memory mapped single word transfers */
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int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
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uint32_t address, uint32_t *value);
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int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
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uint32_t address, uint32_t value);
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/* MEM-AP memory mapped bus block transfers */
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int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
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uint8_t *buffer, int count, uint32_t address);
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int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
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uint8_t *buffer, int count, uint32_t address);
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int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
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uint8_t *buffer, int count, uint32_t address, bool addr_incr);
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int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
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const uint8_t *buffer, int count, uint32_t address);
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int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
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const uint8_t *buffer, int count, uint32_t address);
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int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
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const uint8_t *buffer, int count, uint32_t address, bool addr_incr);
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/* Queued MEM-AP memory mapped single word transfers with selection of ap */
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int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
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uint32_t address, uint32_t *value);
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int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
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uint32_t address, uint32_t value);
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/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
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int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
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uint32_t address, uint32_t *value);
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int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
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uint32_t address, uint32_t value);
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/* Non incrementing buffer functions for accessing fifos */
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int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
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uint8_t *buffer, int count, uint32_t address);
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int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
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const uint8_t *buffer, int count, uint32_t address);
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/* MEM-AP memory mapped bus block transfers with selection of ap */
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int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
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uint8_t *buffer, int count, uint32_t address);
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int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
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uint8_t *buffer, int count, uint32_t address);
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int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
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uint8_t *buffer, int count, uint32_t address);
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int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
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const uint8_t *buffer, int count, uint32_t address);
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int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
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const uint8_t *buffer, int count, uint32_t address);
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int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
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const uint8_t *buffer, int count, uint32_t address);
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/* Initialisation of the debug system, power domains and registers */
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int ahbap_debugport_init(struct adiv5_dap *swjdp);
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/* Probe the AP for ROM Table location */
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int dap_get_debugbase(struct adiv5_dap *dap, int ap,
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uint32_t *dbgbase, uint32_t *apid);
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/* Probe Access Ports to find a particular type */
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int dap_find_ap(struct adiv5_dap *dap,
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enum ap_type type_to_find,
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uint8_t *ap_num_out);
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/* Lookup CoreSight component */
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int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
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uint32_t dbgbase, uint8_t type, uint32_t *addr);
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struct target;
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/* Put debug link into SWD mode */
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int dap_to_swd(struct target *target);
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/* Put debug link into JTAG mode */
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int dap_to_jtag(struct target *target);
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extern const struct command_registration dap_command_handlers[];
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#endif
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