174 lines
5.2 KiB
C
174 lines
5.2 KiB
C
/***************************************************************************
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* Copyright (C) 2009 by David Brownell *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARMV7A_H
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#define ARMV7A_H
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#include "arm_adi_v5.h"
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#include "arm.h"
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#include "armv4_5_mmu.h"
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#include "armv4_5_cache.h"
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#include "arm_dpm.h"
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enum {
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ARM_PC = 15,
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ARM_CPSR = 16
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};
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#define ARMV7_COMMON_MAGIC 0x0A450999
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/* VA to PA translation operations opc2 values*/
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#define V2PCWPR 0
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#define V2PCWPW 1
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#define V2PCWUR 2
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#define V2PCWUW 3
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#define V2POWPR 4
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#define V2POWPW 5
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#define V2POWUR 6
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#define V2POWUW 7
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/* L210/L220 cache controller support */
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struct armv7a_l2x_cache {
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uint32_t base;
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uint32_t way;
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};
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struct armv7a_cachesize {
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uint32_t level_num;
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/* cache dimensionning */
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uint32_t linelen;
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uint32_t associativity;
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uint32_t nsets;
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uint32_t cachesize;
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/* info for set way operation on cache */
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uint32_t index;
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uint32_t index_shift;
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uint32_t way;
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uint32_t way_shift;
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};
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struct armv7a_cache_common {
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int ctype;
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struct armv7a_cachesize d_u_size; /* data cache */
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struct armv7a_cachesize i_size; /* instruction cache */
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int i_cache_enabled;
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int d_u_cache_enabled;
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/* l2 external unified cache if some */
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void *l2_cache;
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int (*flush_all_data_cache)(struct target *target);
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int (*display_cache_info)(struct command_context *cmd_ctx,
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struct armv7a_cache_common *armv7a_cache);
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};
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struct armv7a_mmu_common {
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/* following field mmu working way */
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int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
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uint32_t ttbr0_mask;/* masked to be used */
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uint32_t os_border;
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int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer);
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struct armv7a_cache_common armv7a_cache;
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uint32_t mmu_enabled;
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};
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struct armv7a_common {
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struct arm arm;
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int common_magic;
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struct reg_cache *core_cache;
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struct adiv5_dap dap;
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/* Core Debug Unit */
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struct arm_dpm dpm;
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uint32_t debug_base;
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uint8_t debug_ap;
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uint8_t memory_ap;
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bool memory_ap_available;
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/* mdir */
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uint8_t multi_processor_system;
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uint8_t cluster_id;
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uint8_t cpu_id;
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bool is_armv7r;
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/* cache specific to V7 Memory Management Unit compatible with v4_5*/
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struct armv7a_mmu_common armv7a_mmu;
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int (*examine_debug_reason)(struct target *target);
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int (*post_debug_entry)(struct target *target);
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void (*pre_restore_context)(struct target *target);
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};
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static inline struct armv7a_common *
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target_to_armv7a(struct target *target)
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{
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return container_of(target->arch_info, struct armv7a_common, arm);
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}
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/* register offsets from armv7a.debug_base */
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/* See ARMv7a arch spec section C10.2 */
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#define CPUDBG_DIDR 0x000
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/* See ARMv7a arch spec section C10.3 */
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#define CPUDBG_WFAR 0x018
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/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
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#define CPUDBG_DSCR 0x088
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#define CPUDBG_DRCR 0x090
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#define CPUDBG_PRCR 0x310
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#define CPUDBG_PRSR 0x314
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/* See ARMv7a arch spec section C10.4 */
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#define CPUDBG_DTRRX 0x080
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#define CPUDBG_ITR 0x084
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#define CPUDBG_DTRTX 0x08c
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/* See ARMv7a arch spec section C10.5 */
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#define CPUDBG_BVR_BASE 0x100
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#define CPUDBG_BCR_BASE 0x140
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#define CPUDBG_WVR_BASE 0x180
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#define CPUDBG_WCR_BASE 0x1C0
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#define CPUDBG_VCR 0x01C
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/* See ARMv7a arch spec section C10.6 */
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#define CPUDBG_OSLAR 0x300
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#define CPUDBG_OSLSR 0x304
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#define CPUDBG_OSSRR 0x308
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#define CPUDBG_ECR 0x024
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/* See ARMv7a arch spec section C10.7 */
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#define CPUDBG_DSCCR 0x028
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/* See ARMv7a arch spec section C10.8 */
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#define CPUDBG_AUTHSTATUS 0xFB8
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int armv7a_arch_state(struct target *target);
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int armv7a_identify_cache(struct target *target);
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int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
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int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
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uint32_t *val, int meminfo);
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int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
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int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
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struct armv7a_cache_common *armv7a_cache);
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extern const struct command_registration armv7a_command_handlers[];
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#endif /* ARMV4_5_H */
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