f5657aa76e
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. In the TCL scripts distributed with OpenOCD there are 1700+ lines that should be modified before switching to jimtcl 0.81. Apply the script below on every script in tcl folder. It fixes more than 92% of the lines %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- #!/usr/bin/perl -Wpi my $re_sym = qr{[a-z_][a-z0-9_]*}i; my $re_var = qr{(?:\$|\$::)$re_sym}; my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i; my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)}; my $re_op = qr{<<|>>|[+\-*/&|]}; my $re_expr = qr{( (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item) \s*$re_op\s* (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\)) )}x; # [expr [dict get $regsC100 SYM] + HEXNUM] s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/; # [ expr (EXPR) ] # [ expr EXPR ] # note: $re_expr captures '$3' s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/; s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/; %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6159 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
91 lines
2.6 KiB
INI
91 lines
2.6 KiB
INI
if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME pic32mx
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x30938053
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}
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# default working area is 16384
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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adapter srst delay 100
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jtag_ntrst_delay 100
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#jtag scan chain
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#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
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jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
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#
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# At reset the pic32mx does not allow code execution from RAM
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# we have to setup the BMX registers to allow this.
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# One limitation is that we loose the first 2k of RAM.
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#
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global _PIC32MX_DATASIZE
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global _WORKAREASIZE
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set _PIC32MX_DATASIZE 0x800
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set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}]
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$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
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$_TARGETNAME configure -event reset-init {
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#
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# from reset the pic32 cannot execute code in ram - enable ram execution
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# minimum offset from start of ram is 2k
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#
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global _PIC32MX_DATASIZE
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global _WORKAREASIZE
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# BMXCON set 0 wait state option by clearing BMXWSDRM bit, bit 6
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mww 0xbf882000 0x001f0000
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# BMXDKPBA: 2k kernel data @ 0xa0000000
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mww 0xbf882010 $_PIC32MX_DATASIZE
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# BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
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mww 0xbf882020 $_WORKAREASIZE
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# BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
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mww 0xbf882030 $_WORKAREASIZE
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#
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# Set system clock to 8Mhz if the default clock configuration is set
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#
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# SYSKEY register, make sure OSCCON is locked
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mww 0xbf80f230 0x0
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# SYSKEY register, write unlock sequence
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mww 0xbf80f230 0xaa996655
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mww 0xbf80f230 0x556699aa
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# OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
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mww 0xbf80f004 0x07000000
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# SYSKEY register, relock OSCCON
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mww 0xbf80f230 0x0
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}
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set _FLASHNAME $_CHIPNAME.flash0
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flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
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# add virtual banks for kseg0 and kseg1
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flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
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flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
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set _FLASHNAME $_CHIPNAME.flash1
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flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
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# add virtual banks for kseg0 and kseg1
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flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
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flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
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