c882cb0894
- corrected blocksize handling from GDB "info mem" command (thanks to Øyvind and Spen for these patches) git-svn-id: svn://svn.berlios.de/openocd/trunk@278 b42882b7-edfa-0310-969c-e2dbd0fdcd60
101 lines
3.0 KiB
C
101 lines
3.0 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef AT91SAM7_H
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#define AT91SAM7_H
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#include "flash.h"
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#include "target.h"
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typedef struct at91sam7_flash_bank_s
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{
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u32 working_area;
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u32 working_area_size;
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/* chip id register */
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u32 cidr;
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u16 cidr_ext;
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u16 cidr_nvptyp;
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u16 cidr_arch;
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u16 cidr_sramsiz;
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u16 cidr_nvpsiz;
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u16 cidr_nvpsiz2;
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u16 cidr_eproc;
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u16 cidr_version;
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char * target_name;
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/* flash geometry */
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u16 num_pages;
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u16 pagesize;
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u16 pages_in_lockregion;
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u8 num_erase_regions;
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u8 num_planes;
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u32 *erase_region_info;
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/* nv memory bits */
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u16 num_lockbits;
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u16 lockbits[4];
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u16 num_nvmbits;
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u16 nvmbits;
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u8 securitybit;
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u8 flashmode[4]; /* 0: not init, 1: fmcn for nvbits (1uS), 2: fmcn for flash (1.5uS) */
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/* main clock status */
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u8 mck_valid;
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u32 mck_freq;
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int probed;
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} at91sam7_flash_bank_t;
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/* AT91SAM7 control registers */
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#define DBGU_CIDR 0xFFFFF240
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#define CKGR_MCFR 0xFFFFFC24
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#define CKGR_MCFR_MAINRDY 0x10000
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#define CKGR_PLLR 0xFFFFFC2c
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#define CKGR_PLLR_DIV 0xff
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#define CKGR_PLLR_MUL 0x07ff0000
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#define PMC_MCKR 0xFFFFFC30
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#define PMC_MCKR_CSS 0x03
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#define PMC_MCKR_PRES 0x1c
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/* Flash Controller Commands */
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#define WP 0x01
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#define SLB 0x02
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#define WPL 0x03
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#define CLB 0x04
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#define EA 0x08
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#define SGPB 0x0B
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#define CGPB 0x0D
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#define SSB 0x0F
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/* MC_FSR bit definitions */
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#define MC_FSR_FRDY 1
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#define MC_FSR_EOL 2
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/* AT91SAM7 constants */
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#define RC_FREQ 32000
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/* FLASH_TIMING_MODES */
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#define FMR_TIMING_NONE 0
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#define FMR_TIMING_NVBITS 1
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#define FMR_TIMING_FLASH 2
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#endif /* AT91SAM7_H */
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