d4e195ad1b
Some boards might have RCLK omitted from the JTAG connector and if the interface claims support for it, OpenOCD will end up trying to use RCLK while it's actually impossible. This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch. Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1695 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Mathias Küster <kesmtp@freenet.de>
82 lines
2.7 KiB
INI
82 lines
2.7 KiB
INI
#
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# Texas Instruments DaVinci family: TMS320DM6446
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME dm6446
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}
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# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
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# after JTAG reset until ICEpick is used to route them in.
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set EMU01 "-disable"
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# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
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# needing any ICEpick interaction.
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#set EMU01 "-enable"
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source [find target/icepick.cfg]
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# Subsidiary TAP: unknown ... must enable via ICEpick
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jtag newtap $_CHIPNAME unknown -irlen 8 -disable
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jtag configure $_CHIPNAME.unknown -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 3"
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# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
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jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
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jtag configure $_CHIPNAME.dsp -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 2"
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# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
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if { [info exists ETB_TAPID] } {
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set _ETB_TAPID $ETB_TAPID
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} else {
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set _ETB_TAPID 0x2b900f0f
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}
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jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
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jtag configure $_CHIPNAME.etb -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 1"
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# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
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if { [info exists CPU_TAPID] } {
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set _CPU_TAPID $CPU_TAPID
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} else {
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set _CPU_TAPID 0x07926001
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}
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jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
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jtag configure $_CHIPNAME.arm -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 0"
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# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b70002f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
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jtag configure $_CHIPNAME.jrc -event setup \
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"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
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################
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# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
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# and the ETB memory (4K) are other options, while trace is unused.
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# Little-endian; use the OpenOCD default.
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set _TARGETNAME $_CHIPNAME.arm
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target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
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# be absolutely certain the JTAG clock will work with the worst-case
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# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
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# on the PLL and starts using it. OK to speed up after clock setup.
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adapter_khz 1500
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$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
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arm7_9 fast_memory_access enable
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arm7_9 dcc_downloads enable
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# trace setup
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etm config $_TARGETNAME 16 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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