Tomas Vanek 7d2ea186cf target/riscv: fix 'reset run' after 'reset halt' ... 'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset(). If hw reset line is configured e.g. 'reset_config srst_only' the folowing 'reset run' halts: > gd32v.cpu curstate running > reset halt JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ... > gd32v.cpu curstate halted > reset JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ... > gd32v.cpu curstate halted <<<<---- wrong!!! > reset JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ... > gd32v.cpu curstate running Clear DM_DMCONTROL_HALTREQ when acking reset. Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6961 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com>		2022-05-18 09:03:41 +00:00
..
asm.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
batch.c	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
batch.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
debug_defines.h	riscv: Regenerated debug_defines.h and encoding.h	2021-11-20 14:39:13 +00:00
encoding.h	riscv: Regenerated debug_defines.h and encoding.h	2021-11-20 14:39:13 +00:00
gdb_regs.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
Makefile.am	Add RISC-V support.	2018-07-24 13:07:26 +01:00
opcodes.h	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
program.c	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
program.h	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
riscv_semihosting.c	semihosting: User defined operation, Tcl command exec on host	2022-02-05 21:40:17 +00:00
riscv-011.c	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
riscv-013.c	target/riscv: fix 'reset run' after 'reset halt'	2022-05-18 09:03:41 +00:00
riscv.c	target: Rework 'set' variable of break-/watchpoints	2022-03-19 09:14:39 +00:00
riscv.h	target/riscv: calloc() memory per register.	2021-12-24 15:10:20 +00:00