410 lines
13 KiB
C
410 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* ESP32-S3 target API for OpenOCD *
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* Copyright (C) 2020 Espressif Systems Ltd. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/time_support.h>
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#include <target/target.h>
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#include <target/target_type.h>
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#include <target/smp.h>
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#include "assert.h"
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#include "esp_xtensa_smp.h"
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/*
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This is a JTAG driver for the ESP32_S3, the are two Tensilica cores inside
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the ESP32_S3 chip. For more information please have a look into ESP32_S3 target
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implementation.
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*/
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/* ESP32_S3 memory map */
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#define ESP32_S3_IRAM_LOW 0x40370000
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#define ESP32_S3_IRAM_HIGH 0x403E0000
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#define ESP32_S3_IROM_MASK_LOW 0x40000000
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#define ESP32_S3_IROM_MASK_HIGH 0x40060000
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#define ESP32_S3_DRAM_LOW 0x3FC88000
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#define ESP32_S3_DRAM_HIGH 0x3FD00000
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#define ESP32_S3_RTC_IRAM_LOW 0x600FE000
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#define ESP32_S3_RTC_IRAM_HIGH 0x60100000
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#define ESP32_S3_RTC_DRAM_LOW 0x600FE000
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#define ESP32_S3_RTC_DRAM_HIGH 0x60100000
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#define ESP32_S3_RTC_DATA_LOW 0x50000000
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#define ESP32_S3_RTC_DATA_HIGH 0x50002000
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#define ESP32_S3_EXTRAM_DATA_LOW 0x3D000000
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#define ESP32_S3_EXTRAM_DATA_HIGH 0x3E000000
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#define ESP32_S3_SYS_RAM_LOW 0x60000000UL
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#define ESP32_S3_SYS_RAM_HIGH (ESP32_S3_SYS_RAM_LOW + 0x10000000UL)
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#define ESP32_S3_RTC_SLOW_MEM_BASE ESP32_S3_RTC_DATA_LOW
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/* ESP32_S3 WDT */
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#define ESP32_S3_WDT_WKEY_VALUE 0x50D83AA1
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#define ESP32_S3_TIMG0_BASE 0x6001F000
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#define ESP32_S3_TIMG1_BASE 0x60020000
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#define ESP32_S3_TIMGWDT_CFG0_OFF 0x48
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#define ESP32_S3_TIMGWDT_PROTECT_OFF 0x64
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#define ESP32_S3_TIMG0WDT_CFG0 (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
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#define ESP32_S3_TIMG1WDT_CFG0 (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
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#define ESP32_S3_TIMG0WDT_PROTECT (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
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#define ESP32_S3_TIMG1WDT_PROTECT (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
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#define ESP32_S3_RTCCNTL_BASE 0x60008000
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#define ESP32_S3_RTCWDT_CFG_OFF 0x98
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#define ESP32_S3_RTCWDT_PROTECT_OFF 0xB0
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#define ESP32_S3_SWD_CONF_OFF 0xB0
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#define ESP32_S3_SWD_WPROTECT_OFF 0xB4
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#define ESP32_S3_RTCWDT_CFG (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_CFG_OFF)
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#define ESP32_S3_RTCWDT_PROTECT (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_PROTECT_OFF)
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#define ESP32_S3_SWD_CONF_REG (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_CONF_OFF)
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#define ESP32_S3_SWD_WPROTECT_REG (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_WPROTECT_OFF)
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#define ESP32_S3_SWD_AUTO_FEED_EN_M BIT(31)
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#define ESP32_S3_SWD_WKEY_VALUE 0x8F1D312AU
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#define ESP32_S3_TRACEMEM_BLOCK_SZ 0x4000
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/* ESP32_S3 dport regs */
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#define ESP32_S3_DR_REG_SYSTEM_BASE 0x600c0000
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#define ESP32_S3_SYSTEM_CORE_1_CONTROL_0_REG (ESP32_S3_DR_REG_SYSTEM_BASE + 0x014)
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#define ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN BIT(1)
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/* ESP32_S3 RTC regs */
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#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC)
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#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0
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struct esp32s3_common {
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struct esp_xtensa_smp_common esp_xtensa_smp;
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};
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/* Reset ESP32-S3's peripherals.
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* 1. OpenOCD makes sure the target is halted; if not, tries to halt it.
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* If that fails, tries to reset it (via OCD) and then halt.
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* 2. OpenOCD loads the stub code into RTC_SLOW_MEM.
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* 3. Executes the stub code from address 0x50000004.
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* 4. The stub code changes the reset vector to 0x50000000, and triggers
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* a system reset using RTC_CNTL_SW_SYS_RST bit.
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* 5. Once the PRO CPU is out of reset, it executes the stub code from address 0x50000000.
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* The stub code disables the watchdog, re-enables JTAG and the APP CPU,
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* restores the reset vector, and enters an infinite loop.
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* 6. OpenOCD waits until it can talk to the OCD module again, then halts the target.
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* 7. OpenOCD restores the contents of RTC_SLOW_MEM.
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*
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* End result: all the peripherals except RTC_CNTL are reset, CPU's PC is undefined,
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* PRO CPU is halted, APP CPU is in reset.
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*/
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const uint8_t esp32s3_reset_stub_code[] = {
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#include "../../../contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc"
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};
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static int esp32s3_soc_reset(struct target *target)
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{
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int res;
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struct target_list *head;
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struct xtensa *xtensa;
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LOG_DEBUG("start");
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/* In order to write to peripheral registers, target must be halted first */
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if (target->state != TARGET_HALTED) {
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LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
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xtensa_halt(target);
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res = target_wait_state(target, TARGET_HALTED, 1000);
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if (res != ERROR_OK) {
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LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
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res = xtensa_assert_reset(target);
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if (res != ERROR_OK) {
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LOG_ERROR(
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"Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
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res);
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return res;
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}
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alive_sleep(10);
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xtensa_poll(target);
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bool reset_halt_save = target->reset_halt;
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target->reset_halt = true;
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res = xtensa_deassert_reset(target);
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target->reset_halt = reset_halt_save;
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if (res != ERROR_OK) {
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LOG_ERROR(
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"Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
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res);
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return res;
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}
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alive_sleep(10);
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xtensa_poll(target);
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xtensa_halt(target);
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res = target_wait_state(target, TARGET_HALTED, 1000);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't halt target before SoC reset");
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return res;
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}
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}
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}
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if (target->smp) {
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foreach_smp_target(head, target->smp_targets) {
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xtensa = target_to_xtensa(head->target);
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/* if any of the cores is stalled unstall them */
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if (xtensa_dm_core_is_stalled(&xtensa->dbg_mod)) {
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LOG_TARGET_DEBUG(head->target, "Unstall CPUs before SW reset!");
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res = target_write_u32(target,
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ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG,
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ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF);
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if (res != ERROR_OK) {
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LOG_TARGET_ERROR(head->target, "Failed to unstall CPUs before SW reset!");
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return res;
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}
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break; /* both cores are unstalled now, so exit the loop */
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}
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}
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}
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LOG_DEBUG("Loading stub code into RTC RAM");
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uint8_t slow_mem_save[sizeof(esp32s3_reset_stub_code)];
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/* Save contents of RTC_SLOW_MEM which we are about to overwrite */
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res = target_read_buffer(target, ESP32_S3_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to save contents of RTC_SLOW_MEM (%d)!", res);
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return res;
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}
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/* Write stub code into RTC_SLOW_MEM */
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res = target_write_buffer(target,
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ESP32_S3_RTC_SLOW_MEM_BASE,
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sizeof(esp32s3_reset_stub_code),
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esp32s3_reset_stub_code);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write stub (%d)!", res);
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return res;
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}
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LOG_DEBUG("Resuming the target");
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xtensa = target_to_xtensa(target);
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xtensa->suppress_dsr_errors = true;
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res = xtensa_resume(target, 0, ESP32_S3_RTC_SLOW_MEM_BASE + 4, 0, 0);
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xtensa->suppress_dsr_errors = false;
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to run stub (%d)!", res);
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return res;
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}
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LOG_DEBUG("resume done, waiting for the target to come alive");
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/* Wait for SoC to reset */
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alive_sleep(100);
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int64_t timeout = timeval_ms() + 100;
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bool get_timeout = false;
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while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) {
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alive_sleep(10);
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xtensa_poll(target);
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if (timeval_ms() >= timeout) {
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LOG_TARGET_ERROR(target,
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"Timed out waiting for CPU to be reset, target state=%d",
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target->state);
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get_timeout = true;
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break;
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}
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}
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/* Halt the CPU again */
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LOG_DEBUG("halting the target");
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xtensa_halt(target);
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res = target_wait_state(target, TARGET_HALTED, 1000);
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if (res == ERROR_OK) {
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LOG_DEBUG("restoring RTC_SLOW_MEM");
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res = target_write_buffer(target, ESP32_S3_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
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if (res != ERROR_OK)
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LOG_TARGET_ERROR(target, "Failed to restore contents of RTC_SLOW_MEM (%d)!", res);
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} else {
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LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be halted after SoC reset");
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}
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return get_timeout ? ERROR_TARGET_TIMEOUT : res;
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}
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static int esp32s3_disable_wdts(struct target *target)
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{
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/* TIMG1 WDT */
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int res = target_write_u32(target, ESP32_S3_TIMG0WDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_TIMG0WDT_PROTECT (%d)!", res);
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return res;
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}
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res = target_write_u32(target, ESP32_S3_TIMG0WDT_CFG0, 0);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_TIMG0WDT_CFG0 (%d)!", res);
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return res;
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}
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/* TIMG2 WDT */
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res = target_write_u32(target, ESP32_S3_TIMG1WDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_TIMG1WDT_PROTECT (%d)!", res);
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return res;
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}
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res = target_write_u32(target, ESP32_S3_TIMG1WDT_CFG0, 0);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_TIMG1WDT_CFG0 (%d)!", res);
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return res;
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}
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/* RTC WDT */
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res = target_write_u32(target, ESP32_S3_RTCWDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_RTCWDT_PROTECT (%d)!", res);
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return res;
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}
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res = target_write_u32(target, ESP32_S3_RTCWDT_CFG, 0);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_RTCWDT_CFG (%d)!", res);
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return res;
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}
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/* Enable SWD auto-feed */
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res = target_write_u32(target, ESP32_S3_SWD_WPROTECT_REG, ESP32_S3_SWD_WKEY_VALUE);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_SWD_WPROTECT_REG (%d)!", res);
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return res;
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}
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uint32_t swd_conf_reg = 0;
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res = target_read_u32(target, ESP32_S3_SWD_CONF_REG, &swd_conf_reg);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to read ESP32_S3_SWD_CONF_REG (%d)!", res);
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return res;
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}
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swd_conf_reg |= ESP32_S3_SWD_AUTO_FEED_EN_M;
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res = target_write_u32(target, ESP32_S3_SWD_CONF_REG, swd_conf_reg);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to write ESP32_S3_SWD_CONF_REG (%d)!", res);
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return res;
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}
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return ERROR_OK;
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}
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static int esp32s3_on_halt(struct target *target)
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{
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return esp32s3_disable_wdts(target);
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}
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static int esp32s3_arch_state(struct target *target)
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{
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return ERROR_OK;
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}
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static int esp32s3_virt2phys(struct target *target,
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target_addr_t virtual, target_addr_t *physical)
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{
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if (physical) {
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*physical = virtual;
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return ERROR_OK;
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}
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return ERROR_FAIL;
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}
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static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
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{
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return esp_xtensa_target_init(cmd_ctx, target);
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}
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static const struct xtensa_debug_ops esp32s3_dbg_ops = {
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.queue_enable = xtensa_dm_queue_enable,
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.queue_reg_read = xtensa_dm_queue_reg_read,
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.queue_reg_write = xtensa_dm_queue_reg_write
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};
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static const struct xtensa_power_ops esp32s3_pwr_ops = {
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.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
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.queue_reg_write = xtensa_dm_queue_pwr_reg_write
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};
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static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops = {
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.reset = esp32s3_soc_reset,
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.on_halt = esp32s3_on_halt
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};
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static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
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{
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struct xtensa_debug_module_config esp32s3_dm_cfg = {
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.dbg_ops = &esp32s3_dbg_ops,
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.pwr_ops = &esp32s3_pwr_ops,
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.tap = target->tap,
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.queue_tdi_idle = NULL,
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.queue_tdi_idle_arg = NULL
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};
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struct esp32s3_common *esp32s3 = calloc(1, sizeof(struct esp32s3_common));
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if (!esp32s3) {
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LOG_ERROR("Failed to alloc memory for arch info!");
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return ERROR_FAIL;
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}
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int ret = esp_xtensa_smp_init_arch_info(target,
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&esp32s3->esp_xtensa_smp,
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&esp32s3_dm_cfg,
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&esp32s3_chip_ops);
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if (ret != ERROR_OK) {
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LOG_ERROR("Failed to init arch info!");
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free(esp32s3);
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return ret;
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}
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/* Assume running target. If different, the first poll will fix this. */
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target->state = TARGET_RUNNING;
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target->debug_reason = DBG_REASON_NOTHALTED;
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return ERROR_OK;
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}
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static const struct command_registration esp32s3_command_handlers[] = {
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{
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.usage = "",
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.chain = esp_xtensa_smp_command_handlers,
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},
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{
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.name = "esp32",
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.usage = "",
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.chain = smp_command_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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/** Holds methods for Xtensa targets. */
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struct target_type esp32s3_target = {
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.name = "esp32s3",
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.poll = esp_xtensa_smp_poll,
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.arch_state = esp32s3_arch_state,
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.halt = xtensa_halt,
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.resume = esp_xtensa_smp_resume,
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.step = esp_xtensa_smp_step,
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.assert_reset = esp_xtensa_smp_assert_reset,
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.deassert_reset = esp_xtensa_smp_deassert_reset,
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.soft_reset_halt = esp_xtensa_smp_soft_reset_halt,
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.virt2phys = esp32s3_virt2phys,
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.mmu = xtensa_mmu_is_enabled,
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.read_memory = xtensa_read_memory,
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.write_memory = xtensa_write_memory,
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.read_buffer = xtensa_read_buffer,
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.write_buffer = xtensa_write_buffer,
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.checksum_memory = xtensa_checksum_memory,
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.get_gdb_arch = xtensa_get_gdb_arch,
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.get_gdb_reg_list = xtensa_get_gdb_reg_list,
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.add_breakpoint = esp_xtensa_breakpoint_add,
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.remove_breakpoint = esp_xtensa_breakpoint_remove,
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.add_watchpoint = esp_xtensa_smp_watchpoint_add,
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.remove_watchpoint = esp_xtensa_smp_watchpoint_remove,
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.target_create = esp32s3_target_create,
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.init_target = esp32s3_target_init,
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.examine = xtensa_examine,
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.deinit_target = esp_xtensa_target_deinit,
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.commands = esp32s3_command_handlers,
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};
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