381 lines
13 KiB
C
381 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Generic Xtensa target *
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* Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
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* Copyright (C) 2019 Espressif Systems Ltd. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_XTENSA_H
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#define OPENOCD_TARGET_XTENSA_H
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#include "assert.h"
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#include <target/target.h>
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#include <target/breakpoints.h>
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#include "xtensa_regs.h"
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#include "xtensa_debug_module.h"
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/**
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* @file
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* Holds the interface to Xtensa cores.
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*/
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/* Big-endian vs. little-endian detection */
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#define XT_ISBE(X) ((X)->target->endianness == TARGET_BIG_ENDIAN)
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/* 24-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
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#define XT_INS_BREAK_LE(S, T) (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4))
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#define XT_INS_BREAK_BE(S, T) (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF))
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#define XT_INS_BREAK(X, S, T) (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T))
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/* 16-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
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#define XT_INS_BREAKN_LE(IMM4) (0xF02D | (((IMM4) & 0xF) << 8))
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#define XT_INS_BREAKN_BE(IMM4) (0x0FD2 | (((IMM4) & 0xF) << 12))
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#define XT_INS_BREAKN(X, IMM4) (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4))
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#define XT_ISNS_SZ_MAX 3
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#define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6)
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#define XT_PS_RING_MSK (0x3 << 6)
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#define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3)
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#define XT_PS_CALLINC_MSK (0x3 << 16)
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#define XT_PS_OWB_MSK (0xF << 8)
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#define XT_PS_WOE_MSK BIT(18)
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#define XT_LOCAL_MEM_REGIONS_NUM_MAX 8
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#define XT_AREGS_NUM_MAX 64
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#define XT_USER_REGS_NUM_MAX 256
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#define XT_MEM_ACCESS_NONE 0x0
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#define XT_MEM_ACCESS_READ 0x1
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#define XT_MEM_ACCESS_WRITE 0x2
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#define XT_MAX_TIE_REG_WIDTH (512) /* TIE register file max 4096 bits */
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#define XT_QUERYPKT_RESP_MAX (XT_MAX_TIE_REG_WIDTH * 2 + 1)
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enum xtensa_qerr_e {
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XT_QERR_INTERNAL = 0,
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XT_QERR_FAIL,
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XT_QERR_INVAL,
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XT_QERR_MEM,
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XT_QERR_NUM,
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};
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/* An and ARn registers potentially used as scratch regs */
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enum xtensa_ar_scratch_set_e {
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XT_AR_SCRATCH_A3 = 0,
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XT_AR_SCRATCH_AR3,
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XT_AR_SCRATCH_A4,
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XT_AR_SCRATCH_AR4,
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XT_AR_SCRATCH_NUM
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};
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struct xtensa_keyval_info_s {
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char *chrval;
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int intval;
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};
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enum xtensa_type {
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XT_UNDEF = 0,
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XT_LX,
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};
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struct xtensa_cache_config {
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uint8_t way_count;
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uint32_t line_size;
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uint32_t size;
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int writeback;
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};
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struct xtensa_local_mem_region_config {
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target_addr_t base;
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uint32_t size;
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int access;
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};
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struct xtensa_local_mem_config {
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uint16_t count;
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struct xtensa_local_mem_region_config regions[XT_LOCAL_MEM_REGIONS_NUM_MAX];
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};
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struct xtensa_mmu_config {
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bool enabled;
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uint8_t itlb_entries_count;
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uint8_t dtlb_entries_count;
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};
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struct xtensa_mpu_config {
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bool enabled;
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uint8_t nfgseg;
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uint32_t minsegsize;
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bool lockable;
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bool execonly;
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};
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struct xtensa_irq_config {
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bool enabled;
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uint8_t irq_num;
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};
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struct xtensa_high_prio_irq_config {
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bool enabled;
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uint8_t level_num;
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uint8_t excm_level;
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};
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struct xtensa_debug_config {
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bool enabled;
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uint8_t irq_level;
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uint8_t ibreaks_num;
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uint8_t dbreaks_num;
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uint8_t perfcount_num;
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};
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struct xtensa_tracing_config {
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bool enabled;
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uint32_t mem_sz;
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bool reversed_mem_access;
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};
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struct xtensa_config {
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enum xtensa_type core_type;
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uint8_t aregs_num;
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bool windowed;
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bool coproc;
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bool exceptions;
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struct xtensa_irq_config irq;
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struct xtensa_high_prio_irq_config high_irq;
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struct xtensa_mmu_config mmu;
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struct xtensa_mpu_config mpu;
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struct xtensa_debug_config debug;
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struct xtensa_tracing_config trace;
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struct xtensa_cache_config icache;
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struct xtensa_cache_config dcache;
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struct xtensa_local_mem_config irom;
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struct xtensa_local_mem_config iram;
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struct xtensa_local_mem_config drom;
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struct xtensa_local_mem_config dram;
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struct xtensa_local_mem_config sram;
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struct xtensa_local_mem_config srom;
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};
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typedef uint32_t xtensa_insn_t;
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enum xtensa_stepping_isr_mode {
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XT_STEPPING_ISR_OFF, /* interrupts are disabled during stepping */
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XT_STEPPING_ISR_ON, /* interrupts are enabled during stepping */
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};
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/* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */
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enum xtensa_mode {
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XT_MODE_RING0,
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XT_MODE_RING1,
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XT_MODE_RING2,
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XT_MODE_RING3,
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XT_MODE_ANY /* special value to run algorithm in current core mode */
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};
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struct xtensa_sw_breakpoint {
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struct breakpoint *oocd_bp;
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/* original insn */
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uint8_t insn[XT_ISNS_SZ_MAX];
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/* original insn size */
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uint8_t insn_sz; /* 2 or 3 bytes */
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};
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#define XTENSA_COMMON_MAGIC 0x54E4E555U
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/**
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* Represents a generic Xtensa core.
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*/
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struct xtensa {
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unsigned int common_magic;
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struct xtensa_chip_common *xtensa_chip;
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struct xtensa_config *core_config;
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struct xtensa_debug_module dbg_mod;
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struct reg_cache *core_cache;
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unsigned int total_regs_num;
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unsigned int core_regs_num;
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bool regmap_contiguous;
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unsigned int genpkt_regs_num;
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struct xtensa_reg_desc **contiguous_regs_desc;
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struct reg **contiguous_regs_list;
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/* Per-config Xtensa registers as specified via "xtreg" in xtensa-core*.cfg */
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struct xtensa_reg_desc *optregs;
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unsigned int num_optregs;
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struct reg *empty_regs;
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char qpkt_resp[XT_QUERYPKT_RESP_MAX];
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/* An array of pointers to buffers to backup registers' values while algo is run on target.
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* Size is 'regs_num'. */
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void **algo_context_backup;
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unsigned int eps_dbglevel_idx;
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unsigned int dbregs_num;
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struct target *target;
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bool reset_asserted;
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enum xtensa_stepping_isr_mode stepping_isr_mode;
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struct breakpoint **hw_brps;
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struct watchpoint **hw_wps;
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struct xtensa_sw_breakpoint *sw_brps;
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bool trace_active;
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bool permissive_mode; /* bypass memory checks */
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bool suppress_dsr_errors;
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uint32_t smp_break;
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uint32_t spill_loc;
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unsigned int spill_bytes;
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uint8_t *spill_buf;
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int8_t probe_lsddr32p;
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/* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some
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* time.This is the number of polling periods after which core is considered to be powered
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* off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by
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* SW running on target).*/
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uint8_t come_online_probes_num;
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bool proc_syscall;
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bool halt_request;
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struct xtensa_keyval_info_s scratch_ars[XT_AR_SCRATCH_NUM];
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bool regs_fetched; /* true after first register fetch completed successfully */
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};
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static inline struct xtensa *target_to_xtensa(struct target *target)
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{
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assert(target);
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struct xtensa *xtensa = target->arch_info;
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assert(xtensa->common_magic == XTENSA_COMMON_MAGIC);
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return xtensa;
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}
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int xtensa_init_arch_info(struct target *target,
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struct xtensa *xtensa,
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const struct xtensa_debug_module_config *dm_cfg);
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int xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
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void xtensa_target_deinit(struct target *target);
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static inline bool xtensa_addr_in_mem(const struct xtensa_local_mem_config *mem, uint32_t addr)
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{
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for (unsigned int i = 0; i < mem->count; i++) {
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if (addr >= mem->regions[i].base &&
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addr < mem->regions[i].base + mem->regions[i].size)
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return true;
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}
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return false;
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}
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static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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if (xtensa_addr_in_mem(&xtensa->core_config->drom, addr))
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return true;
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if (xtensa_addr_in_mem(&xtensa->core_config->dram, addr))
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return true;
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if (xtensa_addr_in_mem(&xtensa->core_config->sram, addr))
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return true;
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return false;
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}
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static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, unsigned int reg, uint8_t *data)
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{
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struct xtensa_debug_module *dm = &xtensa->dbg_mod;
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if (!xtensa->core_config->trace.enabled &&
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(reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
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LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
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return ERROR_FAIL;
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}
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return dm->dbg_ops->queue_reg_read(dm, reg, data);
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}
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static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
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{
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struct xtensa_debug_module *dm = &xtensa->dbg_mod;
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if (!xtensa->core_config->trace.enabled &&
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(reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
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LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
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return ERROR_FAIL;
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}
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return dm->dbg_ops->queue_reg_write(dm, reg, data);
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}
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static inline int xtensa_core_status_clear(struct target *target, uint32_t bits)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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return xtensa_dm_core_status_clear(&xtensa->dbg_mod, bits);
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}
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int xtensa_core_status_check(struct target *target);
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int xtensa_examine(struct target *target);
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int xtensa_wakeup(struct target *target);
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int xtensa_smpbreak_set(struct target *target, uint32_t set);
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int xtensa_smpbreak_get(struct target *target, uint32_t *val);
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int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set);
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int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val);
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xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id);
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void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value);
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void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value);
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int xtensa_fetch_all_regs(struct target *target);
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int xtensa_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[],
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int *reg_list_size,
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enum target_register_class reg_class);
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uint32_t xtensa_cause_get(struct target *target);
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void xtensa_cause_clear(struct target *target);
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void xtensa_cause_reset(struct target *target);
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int xtensa_poll(struct target *target);
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void xtensa_on_poll(struct target *target);
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int xtensa_halt(struct target *target);
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int xtensa_resume(struct target *target,
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int current,
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target_addr_t address,
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int handle_breakpoints,
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int debug_execution);
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int xtensa_prepare_resume(struct target *target,
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int current,
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target_addr_t address,
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int handle_breakpoints,
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int debug_execution);
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int xtensa_do_resume(struct target *target);
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int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
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int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
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int xtensa_mmu_is_enabled(struct target *target, int *enabled);
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int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);
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int xtensa_write_memory(struct target *target,
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target_addr_t address,
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uint32_t size,
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uint32_t count,
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const uint8_t *buffer);
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int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer);
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int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum);
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int xtensa_assert_reset(struct target *target);
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int xtensa_deassert_reset(struct target *target);
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int xtensa_soft_reset_halt(struct target *target);
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int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
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int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
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int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
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int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
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void xtensa_set_permissive_mode(struct target *target, bool state);
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const char *xtensa_get_gdb_arch(struct target *target);
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int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p);
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COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target);
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COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_perfmon_enable_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa);
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COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname);
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extern const struct command_registration xtensa_command_handlers[];
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#endif /* OPENOCD_TARGET_XTENSA_H */
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