d265c219b9
Someday revisit various issues: Tempest parts support writing more than one word at a time; for some target firmware it might be necessary to save and restore flash IRQ configuration. (The safest policy is likely to always reset after flash updates.) Plus swap some undesirable TAB characters with SPACE. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
1183 lines
32 KiB
C
1183 lines
32 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/***************************************************************************
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* STELLARIS is tested on LM3S811, LM3S6965
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include "stellaris.h"
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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#define DID0_VER(did0) ((did0 >> 28)&0x07)
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static void stellaris_read_clock_info(struct flash_bank *bank);
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static int stellaris_mass_erase(struct flash_bank *bank);
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static struct {
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uint32_t partno;
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char *partname;
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} StellarisParts[] =
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{
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{0x0001,"LM3S101"},
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{0x0002,"LM3S102"},
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{0x0019,"LM3S300"},
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{0x0011,"LM3S301"},
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{0x001A,"LM3S308"},
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{0x0012,"LM3S310"},
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{0x0013,"LM3S315"},
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{0x0014,"LM3S316"},
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{0x0017,"LM3S317"},
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{0x0015,"LM3S328"},
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{0x002A,"LM3S600"},
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{0x0021,"LM3S601"},
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{0x002B,"LM3S608"},
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{0x0022,"LM3S610"},
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{0x0023,"LM3S611"},
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{0x0024,"LM3S612"},
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{0x0025,"LM3S613"},
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{0x0026,"LM3S615"},
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{0x0028,"LM3S617"},
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{0x0029,"LM3S618"},
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{0x0027,"LM3S628"},
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{0x0038,"LM3S800"},
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{0x0031,"LM3S801"},
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{0x0039,"LM3S808"},
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{0x0032,"LM3S811"},
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{0x0033,"LM3S812"},
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{0x0034,"LM3S815"},
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{0x0036,"LM3S817"},
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{0x0037,"LM3S818"},
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{0x0035,"LM3S828"},
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{0x10BF,"LM3S1110"},
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{0x10C3,"LM3S1133"},
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{0x10C5,"LM3S1138"},
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{0x10C1,"LM3S1150"},
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{0x10C4,"LM3S1162"},
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{0x10C2,"LM3S1165"},
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{0x10C6,"LM3S1332"},
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{0x10BC,"LM3S1435"},
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{0x10BA,"LM3S1439"},
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{0x10BB,"LM3S1512"},
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{0x10C7,"LM3S1538"},
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{0x10DB,"LM3S1601"},
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{0x1006,"LM3S1607"},
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{0x10DA,"LM3S1608"},
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{0x10C0,"LM3S1620"},
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{0x1003,"LM3S1625"},
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{0x1004,"LM3S1626"},
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{0x1005,"LM3S1627"},
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{0x10B3,"LM3S1635"},
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{0x10BD,"LM3S1637"},
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{0x10B9,"LM3S1751"},
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{0x1010,"LM3S1776"},
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{0x1016,"LM3S1811"},
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{0x103D,"LM3S1816"},
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{0x10B4,"LM3S1850"},
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{0x10DD,"LM3S1911"},
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{0x10DC,"LM3S1918"},
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{0x10B7,"LM3S1937"},
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{0x10BE,"LM3S1958"},
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{0x10B5,"LM3S1960"},
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{0x10B8,"LM3S1968"},
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{0x100F,"LM3S1J11"},
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{0x103C,"LM3S1J16"},
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{0x100E,"LM3S1N11"},
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{0x103B,"LM3S1N16"},
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{0x1030,"LM3S1W16"},
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{0x102F,"LM3S1Z16"},
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{0x1051,"LM3S2110"},
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{0x1084,"LM3S2139"},
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{0x1039,"LM3S2276"},
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{0x10A2,"LM3S2410"},
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{0x1059,"LM3S2412"},
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{0x1056,"LM3S2432"},
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{0x105A,"LM3S2533"},
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{0x10E1,"LM3S2601"},
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{0x10E0,"LM3S2608"},
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{0x1033,"LM3S2616"},
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{0x1057,"LM3S2620"},
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{0x1085,"LM3S2637"},
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{0x1053,"LM3S2651"},
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{0x1080,"LM3S2671"},
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{0x1050,"LM3S2678"},
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{0x10A4,"LM3S2730"},
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{0x1052,"LM3S2739"},
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{0x103A,"LM3S2776"},
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{0x106D,"LM3S2793"},
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{0x10E3,"LM3S2911"},
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{0x10E2,"LM3S2918"},
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{0x1054,"LM3S2939"},
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{0x108F,"LM3S2948"},
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{0x1058,"LM3S2950"},
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{0x1055,"LM3S2965"},
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{0x106C,"LM3S2B93"},
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{0x1043,"LM3S3651"},
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{0x1044,"LM3S3739"},
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{0x1049,"LM3S3748"},
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{0x1045,"LM3S3749"},
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{0x1042,"LM3S3826"},
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{0x1041,"LM3S3J26"},
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{0x1040,"LM3S3N26"},
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{0x103F,"LM3S3W26"},
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{0x103E,"LM3S3Z26"},
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{0x1081,"LM3S5632"},
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{0x100C,"LM3S5651"},
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{0x108A,"LM3S5652"},
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{0x104D,"LM3S5656"},
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{0x1091,"LM3S5662"},
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{0x1096,"LM3S5732"},
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{0x1097,"LM3S5737"},
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{0x10A0,"LM3S5739"},
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{0x1099,"LM3S5747"},
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{0x10A7,"LM3S5749"},
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{0x109A,"LM3S5752"},
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{0x109C,"LM3S5762"},
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{0x1069,"LM3S5791"},
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{0x100B,"LM3S5951"},
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{0x104E,"LM3S5956"},
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{0x1068,"LM3S5B91"},
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{0x1009,"LM3S5K31"},
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{0x104A,"LM3S5K36"},
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{0x100A,"LM3S5P31"},
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{0x1048,"LM3S5P36"},
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{0x100D,"LM3S5P51"},
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{0x104C,"LM3S5P56"},
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{0x1007,"LM3S5R31"},
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{0x104B,"LM3S5R36"},
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{0x1047,"LM3S5T36"},
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{0x1046,"LM3S5Y36"},
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{0x10A1,"LM3S6100"},
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{0x1074,"LM3S6110"},
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{0x10A5,"LM3S6420"},
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{0x1082,"LM3S6422"},
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{0x1075,"LM3S6432"},
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{0x1076,"LM3S6537"},
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{0x1071,"LM3S6610"},
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{0x10E7,"LM3S6611"},
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{0x10E6,"LM3S6618"},
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{0x1083,"LM3S6633"},
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{0x108B,"LM3S6637"},
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{0x10A3,"LM3S6730"},
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{0x1077,"LM3S6753"},
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{0x10E9,"LM3S6911"},
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{0x10E8,"LM3S6918"},
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{0x1089,"LM3S6938"},
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{0x1072,"LM3S6950"},
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{0x1078,"LM3S6952"},
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{0x1073,"LM3S6965"},
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{0x1064,"LM3S8530"},
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{0x108E,"LM3S8538"},
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{0x1061,"LM3S8630"},
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{0x1063,"LM3S8730"},
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{0x108D,"LM3S8733"},
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{0x1086,"LM3S8738"},
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{0x1065,"LM3S8930"},
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{0x108C,"LM3S8933"},
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{0x1088,"LM3S8938"},
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{0x10A6,"LM3S8962"},
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{0x1062,"LM3S8970"},
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{0x10D7,"LM3S8971"},
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{0x1067,"LM3S9790"},
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{0x106B,"LM3S9792"},
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{0x1020,"LM3S9997"},
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{0x1066,"LM3S9B90"},
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{0x106A,"LM3S9B92"},
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{0x106E,"LM3S9B95"},
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{0x106F,"LM3S9B96"},
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{0x1018,"LM3S9L97"},
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{0,"Unknown part"}
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};
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static char * StellarisClassname[5] =
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{
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"Sandstorm",
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"Fury",
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"Unknown",
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"DustDevil",
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"Tempest"
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};
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/***************************************************************************
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* openocd command interface *
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***************************************************************************/
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/* flash_bank stellaris <base> <size> 0 0 <target#>
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*/
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FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
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{
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struct stellaris_flash_bank *stellaris_info;
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if (CMD_ARGC < 6)
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{
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LOG_WARNING("incomplete flash_bank stellaris configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
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bank->base = 0x0;
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bank->driver_priv = stellaris_info;
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stellaris_info->target_name = "Unknown target";
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/* part wasn't probed for info yet */
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stellaris_info->did1 = 0;
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/* TODO Specify the main crystal speed in kHz using an optional
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* argument; ditto, the speed of an external oscillator used
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* instead of a crystal. Avoid programming flash using IOSC.
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*/
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return ERROR_OK;
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}
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static int stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
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{
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int printed, device_class;
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struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
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if (stellaris_info->did1 == 0)
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return ERROR_FLASH_BANK_NOT_PROBED;
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/* Read main and master clock freqency register */
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stellaris_read_clock_info(bank);
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if (DID0_VER(stellaris_info->did0) > 0)
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{
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device_class = (stellaris_info->did0 >> 16) & 0xFF;
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}
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else
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{
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device_class = 0;
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}
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printed = snprintf(buf,
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buf_size,
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"\nTI/LMI Stellaris information: Chip is "
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"class %i (%s) %s rev %c%i\n",
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device_class,
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StellarisClassname[device_class],
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stellaris_info->target_name,
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(int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
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(int)((stellaris_info->did0) & 0xFF));
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buf += printed;
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buf_size -= printed;
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printed = snprintf(buf,
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buf_size,
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"did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
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", eproc: %s, ramsize: %ik, flashsize: %ik\n",
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stellaris_info->did1,
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stellaris_info->did1,
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"ARMv7M",
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(int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
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(int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
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buf += printed;
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buf_size -= printed;
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printed = snprintf(buf,
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buf_size,
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"master clock: %ikHz%s, "
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"rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
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(int)(stellaris_info->mck_freq / 1000),
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stellaris_info->mck_desc,
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stellaris_info->rcc,
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stellaris_info->rcc2);
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buf += printed;
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buf_size -= printed;
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if (stellaris_info->num_lockbits > 0)
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{
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printed = snprintf(buf,
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buf_size,
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"pagesize: %" PRIi32 ", pages: %d, "
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"lockbits: %i, pages per lockbit: %i\n",
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stellaris_info->pagesize,
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(unsigned) stellaris_info->num_pages,
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stellaris_info->num_lockbits,
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(unsigned) stellaris_info->pages_in_lockregion);
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buf += printed;
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buf_size -= printed;
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}
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return ERROR_OK;
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}
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/***************************************************************************
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* chip identification and status *
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***************************************************************************/
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/* Set the flash timimg register to match current clocking */
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static void stellaris_set_flash_timing(struct flash_bank *bank)
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{
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struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
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LOG_DEBUG("usecrl = %i",(int)(usecrl));
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target_write_u32(target, SCB_BASE | USECRL, usecrl);
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}
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static const unsigned rcc_xtal[32] = {
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[0x00] = 1000000, /* no pll */
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[0x01] = 1843200, /* no pll */
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[0x02] = 2000000, /* no pll */
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[0x03] = 2457600, /* no pll */
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[0x04] = 3579545,
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[0x05] = 3686400,
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[0x06] = 4000000, /* usb */
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[0x07] = 4096000,
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[0x08] = 4915200,
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[0x09] = 5000000, /* usb */
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[0x0a] = 5120000,
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[0x0b] = 6000000, /* (reset) usb */
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[0x0c] = 6144000,
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[0x0d] = 7372800,
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[0x0e] = 8000000, /* usb */
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[0x0f] = 8192000,
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/* parts before DustDevil use just 4 bits for xtal spec */
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[0x10] = 10000000, /* usb */
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[0x11] = 12000000, /* usb */
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[0x12] = 12288000,
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[0x13] = 13560000,
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[0x14] = 14318180,
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[0x15] = 16000000, /* usb */
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[0x16] = 16384000,
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};
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/** Read clock configuration and set stellaris_info->usec_clocks. */
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static void stellaris_read_clock_info(struct flash_bank *bank)
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{
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struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
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unsigned xtal;
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unsigned long mainfreq;
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target_read_u32(target, SCB_BASE | RCC, &rcc);
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LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
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target_read_u32(target, SCB_BASE | RCC2, &rcc2);
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LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
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target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
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LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
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stellaris_info->rcc = rcc;
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stellaris_info->rcc = rcc2;
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sysdiv = (rcc >> 23) & 0xF;
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usesysdiv = (rcc >> 22) & 0x1;
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bypass = (rcc >> 11) & 0x1;
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oscsrc = (rcc >> 4) & 0x3;
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xtal = (rcc >> 6) & stellaris_info->xtal_mask;
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|
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/* NOTE: post-Sandstorm parts have RCC2 which may override
|
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* parts of RCC ... with more sysdiv options, option for
|
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* 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
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* as zero, so the "use RCC2" flag is always clear.
|
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*/
|
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if (rcc2 & (1 << 31)) {
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sysdiv = (rcc2 >> 23) & 0x3F;
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bypass = (rcc2 >> 11) & 0x1;
|
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oscsrc = (rcc2 >> 4) & 0x7;
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|
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/* FIXME Tempest parts have an additional lsb for
|
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* fractional sysdiv (200 MHz / 2.5 == 80 MHz)
|
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*/
|
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}
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|
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stellaris_info->mck_desc = "";
|
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|
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switch (oscsrc)
|
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{
|
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case 0: /* MOSC */
|
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mainfreq = rcc_xtal[xtal];
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break;
|
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case 1: /* IOSC */
|
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mainfreq = stellaris_info->iosc_freq;
|
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stellaris_info->mck_desc = stellaris_info->iosc_desc;
|
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break;
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case 2: /* IOSC/4 */
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mainfreq = stellaris_info->iosc_freq / 4;
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stellaris_info->mck_desc = stellaris_info->iosc_desc;
|
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break;
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case 3: /* lowspeed */
|
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/* Sandstorm doesn't have this 30K +/- 30% osc */
|
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mainfreq = 30000;
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stellaris_info->mck_desc = " (±30%)";
|
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break;
|
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case 8: /* hibernation osc */
|
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/* not all parts support hibernation */
|
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mainfreq = 32768;
|
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break;
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|
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default: /* NOTREACHED */
|
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mainfreq = 0;
|
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break;
|
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}
|
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|
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/* PLL is used if it's not bypassed; its output is 200 MHz
|
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* even when it runs at 400 MHz (adds divide-by-two stage).
|
|
*/
|
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if (!bypass)
|
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mainfreq = 200000000;
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|
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if (usesysdiv)
|
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stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
|
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else
|
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stellaris_info->mck_freq = mainfreq;
|
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}
|
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|
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/* Read device id register, main clock frequency register and fill in driver info structure */
|
|
static int stellaris_read_part_info(struct flash_bank *bank)
|
|
{
|
|
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
|
|
struct target *target = bank->target;
|
|
uint32_t did0, did1, ver, fam;
|
|
int i;
|
|
|
|
/* Read and parse chip identification register */
|
|
target_read_u32(target, SCB_BASE | DID0, &did0);
|
|
target_read_u32(target, SCB_BASE | DID1, &did1);
|
|
target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
|
|
target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
|
|
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
|
|
did0, did1, stellaris_info->dc0, stellaris_info->dc1);
|
|
|
|
ver = did0 >> 28;
|
|
if ((ver != 0) && (ver != 1))
|
|
{
|
|
LOG_WARNING("Unknown did0 version, cannot identify target");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
if (did1 == 0)
|
|
{
|
|
LOG_WARNING("Cannot identify target as a Stellaris");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
ver = did1 >> 28;
|
|
fam = (did1 >> 24) & 0xF;
|
|
if (((ver != 0) && (ver != 1)) || (fam != 0))
|
|
{
|
|
LOG_WARNING("Unknown did1 version/family.");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
/* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
|
|
* is 12 MHz, but some older parts have 15 MHz. A few data sheets
|
|
* even give _both_ numbers! We'll use current numbers; IOSC is
|
|
* always approximate.
|
|
*
|
|
* For Tempest: IOSC is calibrated, 16 MHz
|
|
*/
|
|
stellaris_info->iosc_freq = 12000000;
|
|
stellaris_info->iosc_desc = " (±30%)";
|
|
stellaris_info->xtal_mask = 0x0f;
|
|
|
|
switch ((did0 >> 28) & 0x7) {
|
|
case 0: /* Sandstorm */
|
|
/*
|
|
* Current (2009-August) parts seem to be rev C2 and use 12 MHz.
|
|
* Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
|
|
* (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
|
|
*/
|
|
if (((did0 >> 8) & 0xff) < 2) {
|
|
stellaris_info->iosc_freq = 15000000;
|
|
stellaris_info->iosc_desc = " (±50%)";
|
|
}
|
|
break;
|
|
case 1:
|
|
switch ((did0 >> 16) & 0xff) {
|
|
case 1: /* Fury */
|
|
break;
|
|
case 4: /* Tempest */
|
|
stellaris_info->iosc_freq = 16000000; /* +/- 1% */
|
|
stellaris_info->iosc_desc = " (±1%)";
|
|
/* FALL THROUGH */
|
|
case 3: /* DustDevil */
|
|
stellaris_info->xtal_mask = 0x1f;
|
|
break;
|
|
default:
|
|
LOG_WARNING("Unknown did0 class");
|
|
}
|
|
break;
|
|
default:
|
|
LOG_WARNING("Unknown did0 version");
|
|
break;
|
|
}
|
|
|
|
for (i = 0; StellarisParts[i].partno; i++)
|
|
{
|
|
if (StellarisParts[i].partno == ((did1 >> 16) & 0xFFFF))
|
|
break;
|
|
}
|
|
|
|
stellaris_info->target_name = StellarisParts[i].partname;
|
|
|
|
stellaris_info->did0 = did0;
|
|
stellaris_info->did1 = did1;
|
|
|
|
stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
|
|
stellaris_info->num_pages = 2 *(1 + (stellaris_info->dc0 & 0xFFFF));
|
|
stellaris_info->pagesize = 1024;
|
|
stellaris_info->pages_in_lockregion = 2;
|
|
|
|
/* REVISIT for at least Tempest parts, read NVMSTAT.FWB too.
|
|
* That exposes a 32-word Flash Write Buffer ... enabling
|
|
* writes of more than one word at a time.
|
|
*/
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/***************************************************************************
|
|
* flash operations *
|
|
***************************************************************************/
|
|
|
|
static int stellaris_protect_check(struct flash_bank *bank)
|
|
{
|
|
struct stellaris_flash_bank *stellaris = bank->driver_priv;
|
|
int status = ERROR_OK;
|
|
unsigned i;
|
|
unsigned page;
|
|
|
|
if (stellaris->did1 == 0)
|
|
return ERROR_FLASH_BANK_NOT_PROBED;
|
|
|
|
for (i = 0; i < (unsigned) bank->num_sectors; i++)
|
|
bank->sectors[i].is_protected = -1;
|
|
|
|
/* Read each Flash Memory Protection Program Enable (FMPPE) register
|
|
* to report any pages that we can't write. Ignore the Read Enable
|
|
* register (FMPRE).
|
|
*/
|
|
for (i = 0, page = 0;
|
|
i < DIV_ROUND_UP(stellaris->num_lockbits, 32u);
|
|
i++) {
|
|
uint32_t lockbits;
|
|
|
|
status = target_read_u32(bank->target,
|
|
SCB_BASE + (i ? (FMPPE0 + 4 * i) : FMPPE),
|
|
&lockbits);
|
|
LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i,
|
|
(unsigned) lockbits, status);
|
|
if (status != ERROR_OK)
|
|
goto done;
|
|
|
|
for (unsigned j = 0; j < 32; j++) {
|
|
unsigned k;
|
|
|
|
for (k = 0; k < stellaris->pages_in_lockregion; k++) {
|
|
if (page >= (unsigned) bank->num_sectors)
|
|
goto done;
|
|
bank->sectors[page++].is_protected =
|
|
!(lockbits & (1 << j));
|
|
}
|
|
}
|
|
}
|
|
|
|
done:
|
|
return status;
|
|
}
|
|
|
|
static int stellaris_erase(struct flash_bank *bank, int first, int last)
|
|
{
|
|
int banknr;
|
|
uint32_t flash_fmc, flash_cris;
|
|
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
|
|
struct target *target = bank->target;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
return ERROR_FLASH_BANK_NOT_PROBED;
|
|
|
|
if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages))
|
|
{
|
|
return ERROR_FLASH_SECTOR_INVALID;
|
|
}
|
|
|
|
if ((first == 0) && (last == ((int)stellaris_info->num_pages-1)))
|
|
{
|
|
return stellaris_mass_erase(bank);
|
|
}
|
|
|
|
/* Refresh flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_timing(bank);
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
|
|
|
|
/* REVISIT this clobbers state set by any halted firmware ...
|
|
* it might want to process those IRQs.
|
|
*/
|
|
|
|
for (banknr = first; banknr <= last; banknr++)
|
|
{
|
|
/* Address is first word in page */
|
|
target_write_u32(target, FLASH_FMA, banknr * stellaris_info->pagesize);
|
|
/* Write erase command */
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while (flash_fmc & FMC_ERASE);
|
|
|
|
/* Check acess violations */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
if (flash_cris & (AMASK))
|
|
{
|
|
LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "", banknr, flash_cris);
|
|
target_write_u32(target, FLASH_CRIS, 0);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
bank->sectors[banknr].is_erased = 1;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stellaris_protect(struct flash_bank *bank, int set, int first, int last)
|
|
{
|
|
uint32_t fmppe, flash_fmc, flash_cris;
|
|
int lockregion;
|
|
|
|
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
|
|
struct target *target = bank->target;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (!set)
|
|
{
|
|
LOG_ERROR("Can't unprotect write-protected pages.");
|
|
/* except by the "recover locked device" procedure ... */
|
|
return ERROR_INVALID_ARGUMENTS;
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
return ERROR_FLASH_BANK_NOT_PROBED;
|
|
|
|
/* lockregions are 2 pages ... must protect [even..odd] */
|
|
if ((first < 0) || (first & 1)
|
|
|| (last < first) || !(last & 1)
|
|
|| (last >= 2 * stellaris_info->num_lockbits))
|
|
{
|
|
LOG_ERROR("Can't protect unaligned or out-of-range sectors.");
|
|
return ERROR_FLASH_SECTOR_INVALID;
|
|
}
|
|
|
|
/* Refresh flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_timing(bank);
|
|
|
|
/* convert from pages to lockregions */
|
|
first /= 2;
|
|
last /= 2;
|
|
|
|
/* FIXME this assumes single FMPPE, for a max of 64K of flash!!
|
|
* Current parts can be much bigger.
|
|
*/
|
|
if (last >= 32) {
|
|
LOG_ERROR("No support yet for protection > 64K");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
target_read_u32(target, SCB_BASE | FMPPE, &fmppe);
|
|
|
|
for (lockregion = first; lockregion <= last; lockregion++)
|
|
fmppe &= ~(1 << lockregion);
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
|
|
|
|
/* REVISIT this clobbers state set by any halted firmware ...
|
|
* it might want to process those IRQs.
|
|
*/
|
|
|
|
LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
|
|
target_write_u32(target, SCB_BASE | FMPPE, fmppe);
|
|
|
|
/* Commit FMPPE */
|
|
target_write_u32(target, FLASH_FMA, 1);
|
|
|
|
/* Write commit command */
|
|
/* REVISIT safety check, since this cannot be undone
|
|
* except by the "Recover a locked device" procedure.
|
|
*/
|
|
LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
|
|
/* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
|
|
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while (flash_fmc & FMC_COMT);
|
|
|
|
/* Check acess violations */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
if (flash_cris & (AMASK))
|
|
{
|
|
LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32 "", flash_cris);
|
|
target_write_u32(target, FLASH_CRIS, 0);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static const uint8_t stellaris_write_code[] =
|
|
{
|
|
/*
|
|
Call with :
|
|
r0 = buffer address
|
|
r1 = destination address
|
|
r2 = bytecount (in) - endaddr (work)
|
|
|
|
Used registers:
|
|
r3 = pFLASH_CTRL_BASE
|
|
r4 = FLASHWRITECMD
|
|
r5 = #1
|
|
r6 = bytes written
|
|
r7 = temp reg
|
|
*/
|
|
0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
|
|
0x08,0x4C, /* ldr r4,FLASHWRITECMD */
|
|
0x01,0x25, /* movs r5, 1 */
|
|
0x00,0x26, /* movs r6, #0 */
|
|
/* mainloop: */
|
|
0x19,0x60, /* str r1, [r3, #0] */
|
|
0x87,0x59, /* ldr r7, [r0, r6] */
|
|
0x5F,0x60, /* str r7, [r3, #4] */
|
|
0x9C,0x60, /* str r4, [r3, #8] */
|
|
/* waitloop: */
|
|
0x9F,0x68, /* ldr r7, [r3, #8] */
|
|
0x2F,0x42, /* tst r7, r5 */
|
|
0xFC,0xD1, /* bne waitloop */
|
|
0x04,0x31, /* adds r1, r1, #4 */
|
|
0x04,0x36, /* adds r6, r6, #4 */
|
|
0x96,0x42, /* cmp r6, r2 */
|
|
0xF4,0xD1, /* bne mainloop */
|
|
/* exit: */
|
|
0xFE,0xE7, /* b exit */
|
|
/* pFLASH_CTRL_BASE: */
|
|
0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
|
|
/* FLASHWRITECMD: */
|
|
0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
|
|
};
|
|
|
|
static int stellaris_write_block(struct flash_bank *bank,
|
|
uint8_t *buffer, uint32_t offset, uint32_t wcount)
|
|
{
|
|
struct target *target = bank->target;
|
|
uint32_t buffer_size = 8192;
|
|
struct working_area *source;
|
|
struct working_area *write_algorithm;
|
|
uint32_t address = bank->base + offset;
|
|
struct reg_param reg_params[3];
|
|
struct armv7m_algorithm armv7m_info;
|
|
int retval = ERROR_OK;
|
|
|
|
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
|
|
bank, buffer, offset, wcount);
|
|
|
|
/* flash write code */
|
|
if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
|
|
{
|
|
LOG_WARNING("no working area available, can't do block memory writes");
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
};
|
|
|
|
target_write_buffer(target, write_algorithm->address,
|
|
sizeof(stellaris_write_code),
|
|
(uint8_t *) stellaris_write_code);
|
|
|
|
/* memory buffer */
|
|
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
|
|
{
|
|
LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08" PRIx32 " source=%p)",
|
|
target, buffer_size, source);
|
|
buffer_size /= 2;
|
|
if (buffer_size <= 256)
|
|
{
|
|
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
|
|
if (write_algorithm)
|
|
target_free_working_area(target, write_algorithm);
|
|
|
|
LOG_WARNING("no large enough working area available, can't do block memory writes");
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
}
|
|
};
|
|
|
|
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
|
|
armv7m_info.core_mode = ARMV7M_MODE_ANY;
|
|
|
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
|
|
|
while (wcount > 0)
|
|
{
|
|
uint32_t thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
|
|
|
|
target_write_buffer(target, source->address, thisrun_count * 4, buffer);
|
|
|
|
buf_set_u32(reg_params[0].value, 0, 32, source->address);
|
|
buf_set_u32(reg_params[1].value, 0, 32, address);
|
|
buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
|
|
LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
|
|
LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
|
|
if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
|
|
{
|
|
LOG_ERROR("error executing stellaris flash write algorithm");
|
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
|
break;
|
|
}
|
|
|
|
buffer += thisrun_count * 4;
|
|
address += thisrun_count * 4;
|
|
wcount -= thisrun_count;
|
|
}
|
|
|
|
target_free_working_area(target, write_algorithm);
|
|
target_free_working_area(target, source);
|
|
|
|
destroy_reg_param(®_params[0]);
|
|
destroy_reg_param(®_params[1]);
|
|
destroy_reg_param(®_params[2]);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
|
|
{
|
|
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
|
|
struct target *target = bank->target;
|
|
uint32_t address = offset;
|
|
uint32_t flash_cris, flash_fmc;
|
|
uint32_t words_remaining = (count / 4);
|
|
uint32_t bytes_remaining = (count & 0x00000003);
|
|
uint32_t bytes_written = 0;
|
|
int retval;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
|
|
bank, buffer, offset, count);
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
return ERROR_FLASH_BANK_NOT_PROBED;
|
|
|
|
if (offset & 0x3)
|
|
{
|
|
LOG_WARNING("offset size must be word aligned");
|
|
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
|
|
}
|
|
|
|
if (offset + count > bank->size)
|
|
return ERROR_FLASH_DST_OUT_OF_BANK;
|
|
|
|
/* Refresh flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_timing(bank);
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
|
|
|
|
/* REVISIT this clobbers state set by any halted firmware ...
|
|
* it might want to process those IRQs.
|
|
*/
|
|
|
|
/* multiple words to be programmed? */
|
|
if (words_remaining > 0)
|
|
{
|
|
/* try using a block write */
|
|
if ((retval = stellaris_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
|
|
{
|
|
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
|
|
{
|
|
/* if block write failed (no sufficient working area),
|
|
* we use normal (slow) single dword accesses */
|
|
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
|
}
|
|
else if (retval == ERROR_FLASH_OPERATION_FAILED)
|
|
{
|
|
/* if an error occured, we examine the reason, and quit */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
|
|
LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
buffer += words_remaining * 4;
|
|
address += words_remaining * 4;
|
|
words_remaining = 0;
|
|
}
|
|
}
|
|
|
|
while (words_remaining > 0)
|
|
{
|
|
if (!(address & 0xff))
|
|
LOG_DEBUG("0x%" PRIx32 "", address);
|
|
|
|
/* Program one word */
|
|
target_write_u32(target, FLASH_FMA, address);
|
|
target_write_buffer(target, FLASH_FMD, 4, buffer);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
|
|
/* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
|
|
/* Wait until write complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
} while (flash_fmc & FMC_WRITE);
|
|
|
|
buffer += 4;
|
|
address += 4;
|
|
words_remaining--;
|
|
}
|
|
|
|
if (bytes_remaining)
|
|
{
|
|
uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
|
|
int i = 0;
|
|
|
|
while (bytes_remaining > 0)
|
|
{
|
|
last_word[i++] = *(buffer + bytes_written);
|
|
bytes_remaining--;
|
|
bytes_written++;
|
|
}
|
|
|
|
if (!(address & 0xff))
|
|
LOG_DEBUG("0x%" PRIx32 "", address);
|
|
|
|
/* Program one word */
|
|
target_write_u32(target, FLASH_FMA, address);
|
|
target_write_buffer(target, FLASH_FMD, 4, last_word);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
|
|
/* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
|
|
/* Wait until write complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
} while (flash_fmc & FMC_WRITE);
|
|
}
|
|
|
|
/* Check access violations */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
if (flash_cris & (AMASK))
|
|
{
|
|
LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stellaris_probe(struct flash_bank *bank)
|
|
{
|
|
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
|
|
int retval;
|
|
|
|
/* If this is a stellaris chip, it has flash; probe() is just
|
|
* to figure out how much is present. Only do it once.
|
|
*/
|
|
if (stellaris_info->did1 != 0)
|
|
return ERROR_OK;
|
|
|
|
/* stellaris_read_part_info() already handled error checking and
|
|
* reporting. Note that it doesn't write, so we don't care about
|
|
* whether the target is halted or not.
|
|
*/
|
|
retval = stellaris_read_part_info(bank);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
/* provide this for the benefit of the NOR flash framework */
|
|
bank->size = 1024 * stellaris_info->num_pages;
|
|
bank->num_sectors = stellaris_info->num_pages;
|
|
bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector));
|
|
for (int i = 0; i < bank->num_sectors; i++)
|
|
{
|
|
bank->sectors[i].offset = i * stellaris_info->pagesize;
|
|
bank->sectors[i].size = stellaris_info->pagesize;
|
|
bank->sectors[i].is_erased = -1;
|
|
bank->sectors[i].is_protected = -1;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int stellaris_mass_erase(struct flash_bank *bank)
|
|
{
|
|
struct target *target = NULL;
|
|
struct stellaris_flash_bank *stellaris_info = NULL;
|
|
uint32_t flash_fmc;
|
|
|
|
stellaris_info = bank->driver_priv;
|
|
target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
return ERROR_FLASH_BANK_NOT_PROBED;
|
|
|
|
/* Refresh flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_timing(bank);
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
|
|
|
|
/* REVISIT this clobbers state set by any halted firmware ...
|
|
* it might want to process those IRQs.
|
|
*/
|
|
|
|
target_write_u32(target, FLASH_FMA, 0);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while (flash_fmc & FMC_MERASE);
|
|
|
|
/* if device has > 128k, then second erase cycle is needed
|
|
* this is only valid for older devices, but will not hurt */
|
|
if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
|
|
{
|
|
target_write_u32(target, FLASH_FMA, 0x20000);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while (flash_fmc & FMC_MERASE);
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(stellaris_handle_mass_erase_command)
|
|
{
|
|
int i;
|
|
|
|
if (CMD_ARGC < 1)
|
|
{
|
|
command_print(CMD_CTX, "stellaris mass_erase <bank>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_bank *bank;
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
|
if (ERROR_OK != retval)
|
|
return retval;
|
|
|
|
if (stellaris_mass_erase(bank) == ERROR_OK)
|
|
{
|
|
/* set all sectors as erased */
|
|
for (i = 0; i < bank->num_sectors; i++)
|
|
{
|
|
bank->sectors[i].is_erased = 1;
|
|
}
|
|
|
|
command_print(CMD_CTX, "stellaris mass erase complete");
|
|
}
|
|
else
|
|
{
|
|
command_print(CMD_CTX, "stellaris mass erase failed");
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static const struct command_registration stellaris_exec_command_handlers[] = {
|
|
{
|
|
.name = "mass_erase",
|
|
.handler = &stellaris_handle_mass_erase_command,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "erase entire device",
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
static const struct command_registration stellaris_command_handlers[] = {
|
|
{
|
|
.name = "stellaris",
|
|
.mode = COMMAND_ANY,
|
|
.help = "Stellaris flash command group",
|
|
.chain = stellaris_exec_command_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
struct flash_driver stellaris_flash = {
|
|
.name = "stellaris",
|
|
.commands = stellaris_command_handlers,
|
|
.flash_bank_command = stellaris_flash_bank_command,
|
|
.erase = stellaris_erase,
|
|
.protect = stellaris_protect,
|
|
.write = stellaris_write,
|
|
.probe = stellaris_probe,
|
|
.auto_probe = stellaris_probe,
|
|
.erase_check = default_flash_mem_blank_check,
|
|
.protect_check = stellaris_protect_check,
|
|
.info = stellaris_info,
|
|
};
|