d376f7f518
Add new AARCH64 target and ARMv8 support files.
This is an instantiation from the cortex_a files but modified to support
64bit ARMv8. Not all features are complete, notably breakpts and single
stepping are not yet implemented.
Currently it lets you halt of the processors, resume, dump cpu
registers,
read/write memory and getting a stack trace with gdb.
> halt
invalid mode value encountered 5
target state: halted
unrecognized psr mode: 0x5
target halted in ARM state due to debug-request, current mode:
UNRECOGNIZED
cpsr: 0x600001c5 pc: 0x00093528
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> targets
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* cpu0 aarch64 little cpu.dap halted
> reg
===== arm v8 registers
(0) r0 (/64): 0x00000000FFFFFFED (dirty)
(1) r1 (/64): 0x00000000F76E4000
(2) r2 (/64): 0x0000000000000000
(3) r3 (/64): 0x0000000000010000
(4) r4 (/64): 0xFFFFFFC06E2939E1
(5) r5 (/64): 0x0000000000000018
(6) r6 (/64): 0x003A699CFB3C8480
(7) r7 (/64): 0x0000000053555555
(8) r8 (/64): 0x00FFFFFFFFFFFFFF
(9) r9 (/64): 0x000000001FFEF992
(10) r10 (/64): 0x0000000000000001
(11) r11 (/64): 0x0000000000000000
(12) r12 (/64): 0x00000000000000F0
(13) r13 (/64): 0x00000000EFDFEAC8
(14) r14 (/64): 0x00000000F6DDA659
(15) r15 (/64): 0x0000000000000000
(16) r16 (/64): 0xFFFFFFC0000F9094
(17) r17 (/64): 0x0000000000000000
(18) r18 (/64): 0x0000000000000000
(19) r19 (/64): 0xFFFFFFC00087C000
(20) r20 (/64): 0x0000000000000002
(21) r21 (/64): 0xFFFFFFC000867C28
(22) r22 (/64): 0xFFFFFFC000916A52
(23) r23 (/64): 0xFFFFFFC00116D8B0
(24) r24 (/64): 0xFFFFFFC000774A0C
(25) r25 (/64): 0x000000008007B000
(26) r26 (/64): 0x000000008007D000
(27) r27 (/64): 0xFFFFFFC000080450
(28) r28 (/64): 0x0000004080000000
(29) r29 (/64): 0xFFFFFFC00087FF20
(30) r30 (/64): 0xFFFFFFC000085114
(31) sp (/64): 0xFFFFFFC00087FF20
(32) pc (/64): 0xFFFFFFC000093528
(33) xPSR (/64): 0x00000000600001C5
And from gdb
(gdb) bt
#0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87
#1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107
#2 0x0000000000000000 in ?? ()
Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618
Signed-off-by: David Ung <david.ung.42@gmail.com>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
205 lines
3.5 KiB
Makefile
205 lines
3.5 KiB
Makefile
if OOCD_TRACE
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OOCD_TRACE_FILES = %D%/oocd_trace.c
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else
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OOCD_TRACE_FILES =
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endif
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%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
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STARTUP_TCL_SRCS += %D%/startup.tcl
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noinst_LTLIBRARIES += %D%/libtarget.la
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%C%_libtarget_la_SOURCES = \
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$(TARGET_CORE_SRC) \
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$(ARM_DEBUG_SRC) \
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$(ARMV4_5_SRC) \
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$(ARMV6_SRC) \
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$(ARMV7_SRC) \
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$(ARM_MISC_SRC) \
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$(AVR32_SRC) \
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$(MIPS32_SRC) \
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$(NDS32_SRC) \
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$(INTEL_IA32_SRC) \
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%D%/avrt.c \
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%D%/dsp563xx.c \
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%D%/dsp563xx_once.c \
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%D%/dsp5680xx.c \
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%D%/hla_target.c
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if TARGET64
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%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
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endif
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TARGET_CORE_SRC = \
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%D%/algorithm.c \
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%D%/register.c \
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%D%/image.c \
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%D%/breakpoints.c \
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%D%/target.c \
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%D%/target_request.c \
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%D%/testee.c \
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%D%/smp.c
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ARMV4_5_SRC = \
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%D%/armv4_5.c \
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%D%/armv4_5_mmu.c \
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%D%/armv4_5_cache.c \
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$(ARM7_9_SRC)
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ARM7_9_SRC = \
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%D%/arm7_9_common.c \
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%D%/arm7tdmi.c \
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%D%/arm720t.c \
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%D%/arm9tdmi.c \
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%D%/arm920t.c \
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%D%/arm966e.c \
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%D%/arm946e.c \
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%D%/arm926ejs.c \
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%D%/feroceon.c
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ARM_MISC_SRC = \
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%D%/fa526.c \
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%D%/xscale.c
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ARMV6_SRC = \
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%D%/arm11.c \
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%D%/arm11_dbgtap.c
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ARMV7_SRC = \
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%D%/armv7m.c \
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%D%/armv7m_trace.c \
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%D%/cortex_m.c \
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%D%/armv7a.c \
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%D%/cortex_a.c \
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%D%/ls1_sap.c
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ARMV8_SRC = \
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%D%/aarch64.c \
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%D%/armv8.c
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ARM_DEBUG_SRC = \
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%D%/arm_dpm.c \
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%D%/arm_jtag.c \
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%D%/arm_disassembler.c \
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%D%/arm_simulator.c \
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%D%/arm_semihosting.c \
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%D%/arm_adi_v5.c \
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%D%/armv7a_cache.c \
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%D%/armv7a_cache_l2x.c \
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%D%/adi_v5_jtag.c \
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%D%/adi_v5_swd.c \
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%D%/embeddedice.c \
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%D%/trace.c \
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%D%/etb.c \
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%D%/etm.c \
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$(OOCD_TRACE_FILES) \
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%D%/etm_dummy.c
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AVR32_SRC = \
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%D%/avr32_ap7k.c \
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%D%/avr32_jtag.c \
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%D%/avr32_mem.c \
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%D%/avr32_regs.c
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MIPS32_SRC = \
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%D%/mips32.c \
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%D%/mips_m4k.c \
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%D%/mips32_pracc.c \
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%D%/mips32_dmaacc.c \
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%D%/mips_ejtag.c
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NDS32_SRC = \
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%D%/nds32.c \
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%D%/nds32_reg.c \
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%D%/nds32_cmd.c \
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%D%/nds32_disassembler.c \
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%D%/nds32_tlb.c \
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%D%/nds32_v2.c \
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%D%/nds32_v3_common.c \
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%D%/nds32_v3.c \
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%D%/nds32_v3m.c \
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%D%/nds32_aice.c
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INTEL_IA32_SRC = \
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%D%/quark_x10xx.c \
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%D%/quark_d20xx.c \
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%D%/lakemont.c \
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%D%/x86_32_common.c
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%C%_libtarget_la_SOURCES += \
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%D%/algorithm.h \
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%D%/arm.h \
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%D%/arm_dpm.h \
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%D%/arm_jtag.h \
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%D%/arm_adi_v5.h \
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%D%/armv7a_cache.h \
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%D%/armv7a_cache_l2x.h \
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%D%/arm_disassembler.h \
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%D%/arm_opcodes.h \
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%D%/arm_simulator.h \
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%D%/arm_semihosting.h \
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%D%/arm7_9_common.h \
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%D%/arm7tdmi.h \
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%D%/arm720t.h \
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%D%/arm9tdmi.h \
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%D%/arm920t.h \
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%D%/arm926ejs.h \
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%D%/arm966e.h \
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%D%/arm946e.h \
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%D%/arm11.h \
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%D%/arm11_dbgtap.h \
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%D%/armv4_5.h \
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%D%/armv4_5_mmu.h \
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%D%/armv4_5_cache.h \
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%D%/armv7a.h \
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%D%/armv7m.h \
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%D%/armv7m_trace.h \
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%D%/armv8.h \
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%D%/avrt.h \
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%D%/dsp563xx.h \
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%D%/dsp563xx_once.h \
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%D%/dsp5680xx.h \
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%D%/breakpoints.h \
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%D%/cortex_m.h \
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%D%/cortex_a.h \
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%D%/aarch64.h \
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%D%/embeddedice.h \
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%D%/etb.h \
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%D%/etm.h \
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%D%/etm_dummy.h \
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%D%/image.h \
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%D%/mips32.h \
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%D%/mips_m4k.h \
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%D%/mips_ejtag.h \
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%D%/mips32_pracc.h \
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%D%/mips32_dmaacc.h \
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%D%/oocd_trace.h \
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%D%/register.h \
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%D%/target.h \
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%D%/target_type.h \
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%D%/trace.h \
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%D%/target_request.h \
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%D%/trace.h \
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%D%/xscale.h \
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%D%/smp.h \
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%D%/avr32_ap7k.h \
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%D%/avr32_jtag.h \
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%D%/avr32_mem.h \
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%D%/avr32_regs.h \
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%D%/nds32.h \
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%D%/nds32_cmd.h \
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%D%/nds32_disassembler.h \
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%D%/nds32_edm.h \
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%D%/nds32_insn.h \
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%D%/nds32_reg.h \
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%D%/nds32_tlb.h \
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%D%/nds32_v2.h \
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%D%/nds32_v3_common.h \
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%D%/nds32_v3.h \
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%D%/nds32_v3m.h \
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%D%/nds32_aice.h \
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%D%/lakemont.h \
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%D%/x86_32_common.h
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include %D%/openrisc/Makefile.am
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