ee8df96b2b
lpc1751, lpc1752, lpc1754, lpc1756, lpc1758, lpc1759 lpc1763, lpc1764, lpc1765, lpc1766, lpc1767, lpc1768, lpc1769 Change-Id: I740b66930cd379c9390f3c1031cdbada747a6ce4 Signed-off-by: Vandra Akos <axos88@gmail.com> Reviewed-on: http://openocd.zylin.com/676 Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Tested-by: jenkins
22 lines
685 B
INI
22 lines
685 B
INI
# !!!!!!!!!!!!
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# ! UNTESTED !
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# !!!!!!!!!!!!
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# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM,
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set CHIPNAME lpc1765
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set CPUTAPID 0x4ba00477
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set CPURAMSIZE 0x8000
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set CPUROMSIZE 0x40000
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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set CCLK 4000
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#Include the main configuration file.
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source [find target/lpc17xx.cfg];
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