da739aa257
Use new target_to_cm3() and target_to_armv7m() inlines, instead of a series of x->arch_info conversions. Remove arch_info, since nothing uses it. Also fix an omission: the Cortex-M3 commands didn't verify that they were operating on that kind of target. Add comment about the ARMv7M version of that omission. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
236 lines
7.6 KiB
C
236 lines
7.6 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARMV7M_COMMON_H
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#define ARMV7M_COMMON_H
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#include "arm_adi_v5.h"
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/* define for enabling armv7 gdb workarounds */
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#if 1
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#define ARMV7_GDB_HACKS
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#endif
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enum armv7m_mode
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{
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ARMV7M_MODE_THREAD = 0,
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ARMV7M_MODE_USER_THREAD = 1,
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ARMV7M_MODE_HANDLER = 2,
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ARMV7M_MODE_ANY = -1
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};
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extern char *armv7m_mode_strings[];
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enum armv7m_regtype
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{
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ARMV7M_REGISTER_CORE_GP,
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ARMV7M_REGISTER_CORE_SP,
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ARMV7M_REGISTER_MEMMAP
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};
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extern char *armv7m_exception_string(int number);
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/* offsets into armv7m core register cache */
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enum
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{
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/* for convenience, the first set of indices match
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* the Cortex-M3 DCRSR selectors
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*/
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ARMV7M_R0,
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ARMV7M_R1,
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ARMV7M_R2,
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ARMV7M_R3,
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ARMV7M_R4,
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ARMV7M_R5,
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ARMV7M_R6,
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ARMV7M_R7,
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ARMV7M_R8,
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ARMV7M_R9,
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ARMV7M_R10,
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ARMV7M_R11,
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ARMV7M_R12,
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ARMV7M_R13,
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ARMV7M_R14,
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ARMV7M_PC = 15,
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ARMV7M_xPSR = 16,
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ARMV7M_MSP,
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ARMV7M_PSP,
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/* this next set of indices is arbitrary */
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ARMV7M_PRIMASK,
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ARMV7M_BASEPRI,
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ARMV7M_FAULTMASK,
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ARMV7M_CONTROL,
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};
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#define ARMV7M_COMMON_MAGIC 0x2A452A45
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typedef struct armv7m_common_s
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{
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int common_magic;
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reg_cache_t *core_cache;
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enum armv7m_mode core_mode;
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int exception_number;
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swjdp_common_t swjdp_info;
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/* Direct processor core register read and writes */
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int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
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int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target_s *target, int num);
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int (*write_core_reg)(struct target_s *target, int num);
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int (*examine_debug_reason)(target_t *target);
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void (*post_debug_entry)(target_t *target);
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void (*pre_restore_context)(target_t *target);
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void (*post_restore_context)(target_t *target);
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} armv7m_common_t;
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static inline struct armv7m_common_s *
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target_to_armv7m(struct target_s *target)
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{
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return target->arch_info;
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}
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typedef struct armv7m_algorithm_s
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{
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int common_magic;
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enum armv7m_mode core_mode;
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} armv7m_algorithm_t;
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typedef struct armv7m_core_reg_s
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{
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uint32_t num;
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enum armv7m_regtype type;
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target_t *target;
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armv7m_common_t *armv7m_common;
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} armv7m_core_reg_t;
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extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
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extern enum armv7m_mode armv7m_number_to_mode(int number);
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extern int armv7m_mode_to_number(enum armv7m_mode mode);
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extern int armv7m_arch_state(struct target_s *target);
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extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
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extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
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extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
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extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
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extern int armv7m_invalidate_core_regs(target_t *target);
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extern int armv7m_restore_context(target_t *target);
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extern int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
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extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
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/* Thumb mode instructions
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*/
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/* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
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* Rd: destination register
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* SYSm: source special register
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*/
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#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
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/* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
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* Rd: source register
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* SYSm: destination special register
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*/
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#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
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/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
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* special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
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* Rd: source register
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* IF:
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*/
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#define I_FLAG 2
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#define F_FLAG 1
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#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
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#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
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/* Breakpoint (Thumb mode) v5 onwards
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* Im: immediate value used by debugger
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*/
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#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16))
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/* Store register (Thumb mode)
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* Rd: source register
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* Rn: base register
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*/
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#define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
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/* Load register (Thumb state)
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* Rd: destination register
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* Rn: base register
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*/
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#define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
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/* Load multiple (Thumb state)
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* Rn: base register
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* List: for each bit in list: store register
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*/
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#define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
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/* Load register with PC relative addressing
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* Rd: register to load
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*/
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#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
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/* Move hi register (Thumb mode)
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* Rd: destination register
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* Rm: source register
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*/
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#define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
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/* No operation (Thumb mode)
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*/
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#define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
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/* Move immediate to register (Thumb state)
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* Rd: destination register
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* Im: 8-bit immediate value
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*/
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#define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
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/* Branch and Exchange
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* Rm: register containing branch target
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*/
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#define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
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/* Branch (Thumb state)
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* Imm: Branch target
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*/
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#define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
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#endif /* ARMV7M_H */
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