dcf977c89a
The ar9331_25mhz_pll_init and ar9331_ddr1_init routines can be used not only for TP-Link MR3020 board, so move them to the common atheros_ar9331.cfg file. Change-Id: I04090856b08151d6bb0f5ef9cc654efae1c81835 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/2999 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
51 lines
1.8 KiB
INI
51 lines
1.8 KiB
INI
if { [info exists CHIPNAME] } {
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set _CHIPNAME $_CHIPNAME
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} else {
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set _CHIPNAME ar9331
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x00000001
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
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proc ar9331_25mhz_pll_init {} {
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mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
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mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
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mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
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;# OUTDIV | REFDIV | DIV_INT
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mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
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;# (disabled?)
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mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
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mww 0xb8050008 0x00008000 ;# remove bypass;
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;# AHB_POST_DIV - ratio 2
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}
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proc ar9331_ddr1_init {} {
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mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
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mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb800000c 0x2 ;# Extended mode register value.
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;# default 0x2 - Reset to weak driver, DLL on
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mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x33 ;# mode reg: remove some bit?
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
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mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
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;# DQ[7:0], DQS_0
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mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
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;# DQ[15:8], DQS_1.
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mww 0xb8000018 0xff ;# DDR read and capture bit mask.
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;# Each bit represents a cycle of valid data.
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}
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