a489058d7b
Only one exported symbol from eCos is included in this patch. The eCos code is left untouched to prevent conflicts with patches currently under review. While there, remove an unused camelcase macro Change-Id: I8d22dec6e243c00665d99a8b8ba00474b4f088db Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6305 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de>
96 lines
4.0 KiB
C
96 lines
4.0 KiB
C
/***************************************************************************
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* Copyright (C) 2015 by Daniel Krebs *
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* Daniel Krebs - github@daniel-krebs.net *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "rtos.h"
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#include "target/armv7m.h"
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#include "rtos_standard_stackings.h"
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/* This works for the M0 and M34 stackings as xPSR is in a fixed
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* location
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*/
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static int64_t rtos_riot_cortex_m_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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int64_t stack_ptr)
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{
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const int XPSR_OFFSET = 0x40;
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return rtos_cortex_m_stack_align(target, stack_data, stacking,
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stack_ptr, XPSR_OFFSET);
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}
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/* see thread_arch.c */
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static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ ARMV7M_R0, 0x24, 32 }, /* r0 */
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{ ARMV7M_R1, 0x28, 32 }, /* r1 */
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{ ARMV7M_R2, 0x2c, 32 }, /* r2 */
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{ ARMV7M_R3, 0x30, 32 }, /* r3 */
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{ ARMV7M_R4, 0x14, 32 }, /* r4 */
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{ ARMV7M_R5, 0x18, 32 }, /* r5 */
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{ ARMV7M_R6, 0x1c, 32 }, /* r6 */
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{ ARMV7M_R7, 0x20, 32 }, /* r7 */
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{ ARMV7M_R8, 0x04, 32 }, /* r8 */
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{ ARMV7M_R9, 0x08, 32 }, /* r9 */
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{ ARMV7M_R10, 0x0c, 32 }, /* r10 */
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{ ARMV7M_R11, 0x10, 32 }, /* r11 */
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{ ARMV7M_R12, 0x34, 32 }, /* r12 */
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{ ARMV7M_R13, -2, 32 }, /* sp */
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{ ARMV7M_R14, 0x38, 32 }, /* lr */
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{ ARMV7M_PC, 0x3c, 32 }, /* pc */
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{ ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
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};
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const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
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0x44, /* stack_registers_size */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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rtos_riot_cortex_m_stack_align, /* stack_alignment */
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rtos_riot_cortex_m0_stack_offsets /* register_offsets */
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};
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/* see thread_arch.c */
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static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ ARMV7M_R0, 0x24, 32 }, /* r0 */
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{ ARMV7M_R1, 0x28, 32 }, /* r1 */
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{ ARMV7M_R2, 0x2c, 32 }, /* r2 */
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{ ARMV7M_R3, 0x30, 32 }, /* r3 */
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{ ARMV7M_R4, 0x04, 32 }, /* r4 */
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{ ARMV7M_R5, 0x08, 32 }, /* r5 */
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{ ARMV7M_R6, 0x0c, 32 }, /* r6 */
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{ ARMV7M_R7, 0x10, 32 }, /* r7 */
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{ ARMV7M_R8, 0x14, 32 }, /* r8 */
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{ ARMV7M_R9, 0x18, 32 }, /* r9 */
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{ ARMV7M_R10, 0x1c, 32 }, /* r10 */
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{ ARMV7M_R11, 0x20, 32 }, /* r11 */
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{ ARMV7M_R12, 0x34, 32 }, /* r12 */
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{ ARMV7M_R13, -2, 32 }, /* sp */
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{ ARMV7M_R14, 0x38, 32 }, /* lr */
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{ ARMV7M_PC, 0x3c, 32 }, /* pc */
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{ ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
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};
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const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
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0x44, /* stack_registers_size */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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rtos_riot_cortex_m_stack_align, /* stack_alignment */
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rtos_riot_cortex_m34_stack_offsets /* register_offsets */
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};
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