b5d2b1224f
Hypervisor mode is present only if the optional virtualization extensions are available. Moreover, virtualization extensions require that also security extensions are implemented. Add the required infrastructure for the shadowed registers in hypervisor mode. Make monitor shadowed registers visible in hypervisor mode too. Make hypervisor shadowed registers visible in hypervisor mode only. Check during cortex_a examine if virtualization extensions are present and then conditionally enable the visibility of both hypervisor and monitor modes shadowed registers. Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5261 Tested-by: jenkins
50 lines
2.6 KiB
C
50 lines
2.6 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2009 by Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARMV4_5_H
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#define OPENOCD_TARGET_ARMV4_5_H
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/* This stuff "knows" that its callers aren't talking
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* to microcontroller profile (current Cortex-M) parts.
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* We want to phase it out so core code can be shared.
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*/
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/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
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* index into the armv4_5_core_reg_map array. Its remaining users are
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* remnants which could as easily walk * the register cache directly as
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* use the expensive ARMV4_5_CORE_REG_MODE() macro.
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*/
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int arm_mode_to_number(enum arm_mode mode);
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enum arm_mode armv4_5_number_to_mode(int number);
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extern const int armv4_5_core_reg_map[9][17];
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#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
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(cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]])
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/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
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enum { ARMV4_5_CPSR = 31, };
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#endif /* OPENOCD_TARGET_ARMV4_5_H */
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