f5657aa76e
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. In the TCL scripts distributed with OpenOCD there are 1700+ lines that should be modified before switching to jimtcl 0.81. Apply the script below on every script in tcl folder. It fixes more than 92% of the lines %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- #!/usr/bin/perl -Wpi my $re_sym = qr{[a-z_][a-z0-9_]*}i; my $re_var = qr{(?:\$|\$::)$re_sym}; my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i; my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)}; my $re_op = qr{<<|>>|[+\-*/&|]}; my $re_expr = qr{( (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item) \s*$re_op\s* (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\)) )}x; # [expr [dict get $regsC100 SYM] + HEXNUM] s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/; # [ expr (EXPR) ] # [ expr EXPR ] # note: $re_expr captures '$3' s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/; s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/; %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6159 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
165 lines
3.6 KiB
INI
165 lines
3.6 KiB
INI
# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
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#
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# use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config trst_and_srst srst_pulls_trst
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cap7
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x40700f0f
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -event reset-start {
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# start off real slow when we're running off internal RC oscillator
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adapter speed 32
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}
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proc peek32 {address} {
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mem2array t 32 $address 1
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return $t(0)
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}
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# Wait for an expression to be true with a timeout
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proc wait_state {expression} {
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for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
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if {[uplevel 1 $expression] == 0} {
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return
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}
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}
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return -code 1 "Timed out"
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}
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# Use a global variable here to be able to tinker interactively with
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# post reset jtag frequency.
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global post_reset_khz
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# Danger!!!! Even 16MHz kinda works with this target, but
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# it needs to be as low as 2000kHz to be stable.
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set post_reset_khz 2000
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$_TARGETNAME configure -event reset-init {
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echo "Configuring master clock"
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# disable watchdog
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mww 0xfffffd44 0xff008000
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# enable user reset
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mww 0xfffffd08 0xa5000001
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# Enable main oscillator
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mww 0xFFFFFc20 0x00000f01
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wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
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# Set PLLA to 96MHz
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mww 0xFFFFFc28 0x20072801
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wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
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# Select prescaler
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mww 0xFFFFFC30 0x00000004
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wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
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# Select master clock to 48MHz
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mww 0xFFFFFC30 0x00000006
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wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
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echo "Master clock ok."
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# Now that we're up and running, crank up speed!
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global post_reset_khz ; adapter speed $post_reset_khz
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echo "Configuring the SDRAM controller..."
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# Configure EBI Chip select for SDRAM
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mww 0xFFFFEF30 0x00000102
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# Enable clock on EBI PIOs
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mww 0xFFFFFC10 0x00000004
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# Configure PIO for SDRAM
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mww 0xFFFFF470 0xFFFF0000
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mww 0xFFFFF474 0x00000000
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mww 0xFFFFF404 0xFFFF0000
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# Configure SDRAMC CR
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mww 0xFFFFEA08 0xA63392F9
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# NOP command
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mww 0xFFFFEA00 0x1
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mww 0x20000000 0
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# Precharge All Banks command
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mww 0xFFFFEA00 0x2
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mww 0x20000000 0
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# Set 1st CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000010 0x00000001
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# Set 2nd CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000020 0x00000002
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# Set 3rd CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000030 0x00000003
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# Set 4th CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000040 0x00000004
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# Set 5th CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000050 0x00000005
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# Set 6th CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000060 0x00000006
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# Set 7th CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000070 0x00000007
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# Set 8th CBR
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mww 0xFFFFEA00 0x00000004
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mww 0x20000080 0x00000008
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# Set LMR operation
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mww 0xFFFFEA00 0x00000003
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# Perform LMR burst=1, lat=2
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mww 0x20000020 0xCAFEDEDE
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# Set Refresh Timer
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mww 0xFFFFEA04 0x00000203
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# Set Normal mode
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mww 0xFFFFEA00 0x00000000
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mww 0x20000000 0x00000000
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#remap internal memory at address 0x0
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mww 0xffffef00 0x3
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echo "SDRAM configuration ok."
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}
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$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
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arm7_9 dcc_downloads enable
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arm7_9 fast_memory_access enable
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#set _FLASHNAME $_CHIPNAME.flash
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#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
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