4946925bea
Search and destroy lingering cases where the ARRAY_SIZE macro should be used to convey more intrinsic meaning in the OpenOCD code.
289 lines
8.2 KiB
C
289 lines
8.2 KiB
C
/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "mips32.h"
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#include "mips_ejtag.h"
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int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch)
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{
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struct jtag_tap *tap;
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tap = ejtag_info->tap;
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if (tap == NULL)
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return ERROR_FAIL;
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if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr)
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{
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struct scan_field field;
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uint8_t t[4];
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field.tap = tap;
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field.num_bits = tap->ir_length;
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field.out_value = t;
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buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
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field.in_value = NULL;
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jtag_add_ir_scan(1, &field, jtag_get_end_state());
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}
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return ERROR_OK;
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}
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int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
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{
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struct scan_field field;
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jtag_set_end_state(TAP_IDLE);
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
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field.tap = ejtag_info->tap;
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field.num_bits = 32;
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field.out_value = NULL;
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field.in_value = (void*)idcode;
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jtag_add_dr_scan(1, &field, jtag_get_end_state());
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if (jtag_execute_queue() != ERROR_OK)
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{
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LOG_ERROR("register read failed");
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}
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return ERROR_OK;
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}
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int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
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{
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struct scan_field field;
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jtag_set_end_state(TAP_IDLE);
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
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field.tap = ejtag_info->tap;
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field.num_bits = 32;
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field.out_value = NULL;
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field.in_value = (void*)impcode;
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jtag_add_dr_scan(1, &field, jtag_get_end_state());
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if (jtag_execute_queue() != ERROR_OK)
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{
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LOG_ERROR("register read failed");
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}
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return ERROR_OK;
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}
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int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
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{
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struct jtag_tap *tap;
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tap = ejtag_info->tap;
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if (tap == NULL)
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return ERROR_FAIL;
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struct scan_field field;
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uint8_t t[4], r[4];
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int retval;
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field.tap = tap;
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field.num_bits = 32;
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field.out_value = t;
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buf_set_u32(field.out_value, 0, field.num_bits, *data);
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field.in_value = r;
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jtag_add_dr_scan(1, &field, jtag_get_end_state());
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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LOG_ERROR("register read failed");
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return retval;
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}
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*data = buf_get_u32(field.in_value, 0, 32);
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keep_alive();
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return ERROR_OK;
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}
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int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
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{
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uint32_t code[] = {
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MIPS32_MTC0(1,31,0), /* move $1 to COP0 DeSave */
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MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */
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MIPS32_ORI(1,1,0x0100), /* set SSt bit in debug reg */
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MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */
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MIPS32_MFC0(1,31,0), /* move COP0 DeSave to $1 */
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MIPS32_NOP,
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MIPS32_B(NEG16(7)),
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MIPS32_NOP,
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};
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mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
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0, NULL, 0, NULL, 1);
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return ERROR_OK;
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}
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int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
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{
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uint32_t code[] = {
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MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
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MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
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MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
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MIPS32_SW(1,0,15), /* sw $1,($15) */
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MIPS32_SW(2,0,15), /* sw $2,($15) */
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MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */
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MIPS32_LUI(2,0xFFFF), /* $2 = 0xfffffeff */
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MIPS32_ORI(2,2,0xFEFF),
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MIPS32_AND(1,1,2),
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MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */
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MIPS32_LW(2,0,15),
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MIPS32_LW(1,0,15),
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(15)),
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MIPS32_NOP,
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};
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mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
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0, NULL, 0, NULL, 1);
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return ERROR_OK;
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}
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int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
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{
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if (enable_step)
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return mips_ejtag_step_enable(ejtag_info);
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return mips_ejtag_step_disable(ejtag_info);
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}
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int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
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{
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uint32_t ejtag_ctrl;
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jtag_set_end_state(TAP_IDLE);
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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/* set debug break bit */
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ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* break bit will be cleared by hardware */
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
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if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
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LOG_DEBUG("Failed to enter Debug Mode!");
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return ERROR_OK;
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}
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int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
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{
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uint32_t inst;
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inst = MIPS32_DRET;
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/* execute our dret instruction */
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mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
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return ERROR_OK;
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}
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int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
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{
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/* read ejtag ECR */
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uint32_t code[] = {
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MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
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MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
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MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
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MIPS32_SW(1,0,15), /* sw $1,($15) */
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MIPS32_SW(2,0,15), /* sw $2,($15) */
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MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */
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MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
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MIPS32_MFC0(2,23,0), /* move COP0 Debug to $2 */
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MIPS32_SW(2,0,1),
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MIPS32_LW(2,0,15),
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MIPS32_LW(1,0,15),
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MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
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MIPS32_NOP,
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MIPS32_B(NEG16(14)),
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MIPS32_NOP,
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};
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mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
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0, NULL, 1, debug_reg, 1);
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return ERROR_OK;
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}
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int mips_ejtag_init(struct mips_ejtag *ejtag_info)
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{
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uint32_t ejtag_version;
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mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
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LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
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/* get ejtag version */
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ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
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switch (ejtag_version)
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{
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case 0:
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LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
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break;
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case 1:
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LOG_DEBUG("EJTAG: Version 2.5 Detected");
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break;
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case 2:
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LOG_DEBUG("EJTAG: Version 2.6 Detected");
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break;
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case 3:
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LOG_DEBUG("EJTAG: Version 3.1 Detected");
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break;
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default:
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LOG_DEBUG("EJTAG: Unknown Version Detected");
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break;
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}
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LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
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ejtag_info->impcode & (1 << 28) ? " R3k": " R4k",
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ejtag_info->impcode & (1 << 24) ? " DINT": "",
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ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
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ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
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ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
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ejtag_info->impcode & (1 << 14) ? " noDMA": " DMA",
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ejtag_info->impcode & (1 << 0) ? " MIPS64": " MIPS32"
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);
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if ((ejtag_info->impcode & (1 << 14)) == 0)
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LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
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/* set initial state for ejtag control reg */
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ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
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return ERROR_OK;
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}
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