47b8cf8420
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
58 lines
2.6 KiB
C
58 lines
2.6 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARMV4_5_MMU_H
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#define OPENOCD_TARGET_ARMV4_5_MMU_H
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#include "armv4_5_cache.h"
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struct target;
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struct armv4_5_mmu_common {
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int (*get_ttb)(struct target *target, uint32_t *result);
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int (*read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int (*write_memory)(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer);
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int (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
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int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
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struct armv4_5_cache_common armv4_5_cache;
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int has_tiny_pages;
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int mmu_enabled;
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};
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int armv4_5_mmu_translate_va(struct target *target,
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struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va,
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uint32_t *cb, uint32_t *val);
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int armv4_5_mmu_read_physical(struct target *target,
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struct armv4_5_mmu_common *armv4_5_mmu,
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uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int armv4_5_mmu_write_physical(struct target *target,
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struct armv4_5_mmu_common *armv4_5_mmu,
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uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
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enum {
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ARMV4_5_MMU_ENABLED = 0x1,
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ARMV4_5_ALIGNMENT_CHECK = 0x2,
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ARMV4_5_MMU_S_BIT = 0x100,
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ARMV4_5_MMU_R_BIT = 0x200
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};
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#endif /* OPENOCD_TARGET_ARMV4_5_MMU_H */
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