Tim Newsome 41147e6fcd Implement CRC32 algorithm for RISC-V. ... Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01 Reviewed-on: http://openocd.zylin.com/6076 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins		2021-03-19 21:58:17 +00:00
..
asm.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
batch.c	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
batch.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
debug_defines.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
encoding.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
gdb_regs.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
Makefile.am	Add RISC-V support.	2018-07-24 13:07:26 +01:00
opcodes.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
program.c	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
program.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
riscv_semihosting.c	semihosting: print the semihosting operation id	2020-11-07 20:50:16 +00:00
riscv-011.c	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
riscv-013.c	openocd: fix doxygen parameters of functions	2021-01-13 11:33:53 +00:00
riscv.c	Implement CRC32 algorithm for RISC-V.	2021-03-19 21:58:17 +00:00
riscv.h	target/register: use an array of uint8_t for register's value	2020-12-05 23:18:37 +00:00