f3e6f584f1
Remove the now vestigial <flash/flash.h> header from the tree, replacing a few references with <flash/nor/core.h>
100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef STM32X_H
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#define STM32X_H
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struct stm32x_options
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{
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uint16_t RDP;
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uint16_t user_options;
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uint16_t protection[4];
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};
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struct stm32x_flash_bank
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{
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struct stm32x_options option_bytes;
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struct working_area *write_algorithm;
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int ppage_size;
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int probed;
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};
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/* stm32x register locations */
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#define STM32_FLASH_ACR 0x40022000
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#define STM32_FLASH_KEYR 0x40022004
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#define STM32_FLASH_OPTKEYR 0x40022008
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#define STM32_FLASH_SR 0x4002200C
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#define STM32_FLASH_CR 0x40022010
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#define STM32_FLASH_AR 0x40022014
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#define STM32_FLASH_OBR 0x4002201C
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#define STM32_FLASH_WRPR 0x40022020
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/* option byte location */
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#define STM32_OB_RDP 0x1FFFF800
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#define STM32_OB_USER 0x1FFFF802
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#define STM32_OB_DATA0 0x1FFFF804
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#define STM32_OB_DATA1 0x1FFFF806
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#define STM32_OB_WRP0 0x1FFFF808
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#define STM32_OB_WRP1 0x1FFFF80A
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#define STM32_OB_WRP2 0x1FFFF80C
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#define STM32_OB_WRP3 0x1FFFF80E
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/* FLASH_CR register bits */
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#define FLASH_PG (1 << 0)
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#define FLASH_PER (1 << 1)
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#define FLASH_MER (1 << 2)
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#define FLASH_OPTPG (1 << 4)
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#define FLASH_OPTER (1 << 5)
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#define FLASH_STRT (1 << 6)
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#define FLASH_LOCK (1 << 7)
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#define FLASH_OPTWRE (1 << 9)
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/* FLASH_SR register bits */
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#define FLASH_BSY (1 << 0)
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#define FLASH_PGERR (1 << 2)
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#define FLASH_WRPRTERR (1 << 4)
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#define FLASH_EOP (1 << 5)
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/* STM32_FLASH_OBR bit definitions (reading) */
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#define OPT_ERROR 0
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#define OPT_READOUT 1
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#define OPT_RDWDGSW 2
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#define OPT_RDRSTSTOP 3
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#define OPT_RDRSTSTDBY 4
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/* register unlock keys */
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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struct stm32x_mem_layout {
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uint32_t sector_start;
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uint32_t sector_size;
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};
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#endif /* STM32X_H */
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