a8b1bd8376
As stated in ARM v8-A Architecture Reference Manual (ARM DDI 0487E.a)
in Chapter H4.3 DCC and ITR access modes:
Writes to EDITR trigger the instruction to be executed if the PE
is in Debug state:
- If the PE is in AArch64 state, this is an A64 instruction.
- If the PE is in AArch32 state, this is a T32 instruction
But in armv8_opcodes specifically in t32_opcodes we were using some
A32 instructions for HLT, LDRx and STRx opcodes.
Using the correct LDRx and STRx opcodes, fixes 16 and 8 bits memory access
when the PE is in AArch32 state.
Change-Id: Ib1acbdd4966297e7b069569bcb8deea3c3993615
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5346
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
221 lines
8.0 KiB
C
221 lines
8.0 KiB
C
/*
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* Copyright (C) 2015 by pierrr kuo
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* vichy.kuo@gmail.com
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef OPENOCD_TARGET_ARMV8_OPCODES_H
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#define OPENOCD_TARGET_ARMV8_OPCODES_H
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#include "arm_opcodes.h"
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#define SYSTEM_CUREL_MASK 0xC0
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#define SYSTEM_CUREL_SHIFT 6
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#define SYSTEM_CUREL_EL0 0x0
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#define SYSTEM_CUREL_EL1 0x1
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#define SYSTEM_CUREL_EL2 0x2
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#define SYSTEM_CUREL_EL3 0x3
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#define SYSTEM_CUREL_NONCH 0xF
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#define SYSTEM_AARCH64 0x1
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#define SYSTEM_AAR64_MODE_EL0t 0x0
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#define SYSTEM_AAR64_MODE_EL1t 0x4
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#define SYSTEM_AAR64_MODE_EL1h 0x5
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#define SYSTEM_AAR64_MODE_EL2t 0x8
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#define SYSTEM_AAR64_MODE_EL2h 0x9
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#define SYSTEM_AAR64_MODE_EL3t 0xC
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#define SYSTEM_AAR64_MODE_EL3h 0xd
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#define SYSTEM_DAIF 0b1101101000010001
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#define SYSTEM_DAIF_MASK 0x3C0
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#define SYSTEM_DAIF_SHIFT 6
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#define SYSTEM_ELR_EL1 0b1100001000000001
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#define SYSTEM_ELR_EL2 0b1110001000000001
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#define SYSTEM_ELR_EL3 0b1111001000000001
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#define SYSTEM_SCTLR_EL1 0b1100000010000000
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#define SYSTEM_SCTLR_EL2 0b1110000010000000
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#define SYSTEM_SCTLR_EL3 0b1111000010000000
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#define SYSTEM_FPCR 0b1101101000100000
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#define SYSTEM_FPSR 0b1101101000100001
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#define SYSTEM_DAIF 0b1101101000010001
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#define SYSTEM_NZCV 0b1101101000010000
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#define SYSTEM_SP_EL0 0b1100001000001000
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#define SYSTEM_SP_EL1 0b1110001000001000
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#define SYSTEM_SP_EL2 0b1111001000001000
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#define SYSTEM_SP_SEL 0b1100001000010000
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#define SYSTEM_SPSR_ABT 0b1110001000011001
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#define SYSTEM_SPSR_FIQ 0b1110001000011011
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#define SYSTEM_SPSR_IRQ 0b1110001000011000
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#define SYSTEM_SPSR_UND 0b1110001000011010
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#define SYSTEM_SPSR_EL1 0b1100001000000000
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#define SYSTEM_SPSR_EL2 0b1110001000000000
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#define SYSTEM_SPSR_EL3 0b1111001000000000
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#define SYSTEM_ISR_EL1 0b1100011000001000
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#define SYSTEM_DBG_DSPSR_EL0 0b1101101000101000
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#define SYSTEM_DBG_DLR_EL0 0b1101101000101001
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#define SYSTEM_DBG_DTRRX_EL0 0b1001100000101000
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#define SYSTEM_DBG_DTRTX_EL0 0b1001100000101000
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#define SYSTEM_DBG_DBGDTR_EL0 0b1001100000100000
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#define SYSTEM_CCSIDR 0b1100100000000000
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#define SYSTEM_CLIDR 0b1100100000000001
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#define SYSTEM_CSSELR 0b1101000000000000
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#define SYSTEM_CTYPE 0b1101100000000001
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#define SYSTEM_CTR 0b1101100000000001
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#define SYSTEM_DCCISW 0b0100001111110010
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#define SYSTEM_DCCSW 0b0100001111010010
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#define SYSTEM_ICIVAU 0b0101101110101001
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#define SYSTEM_DCCVAU 0b0101101111011001
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#define SYSTEM_DCCIVAC 0b0101101111110001
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#define SYSTEM_MPIDR 0b1100000000000101
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#define SYSTEM_TCR_EL1 0b1100000100000010
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#define SYSTEM_TCR_EL2 0b1110000100000010
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#define SYSTEM_TCR_EL3 0b1111000100000010
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#define SYSTEM_TTBR0_EL1 0b1100000100000000
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#define SYSTEM_TTBR0_EL2 0b1110000100000000
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#define SYSTEM_TTBR0_EL3 0b1111000100000000
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#define SYSTEM_TTBR1_EL1 0b1100000100000001
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/* ARMv8 address translation */
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#define SYSTEM_PAR_EL1 0b1100001110100000
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#define SYSTEM_ATS12E0R 0b0110001111000110
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#define SYSTEM_ATS12E1R 0b0110001111000100
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#define SYSTEM_ATS1E2R 0b0110001111000000
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#define SYSTEM_ATS1E3R 0b0111001111000000
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/* fault status and fault address */
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#define SYSTEM_FAR_EL1 0b1100001100000000
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#define SYSTEM_FAR_EL2 0b1110001100000000
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#define SYSTEM_FAR_EL3 0b1111001100000000
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#define SYSTEM_ESR_EL1 0b1100001010010000
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#define SYSTEM_ESR_EL2 0b1110001010010000
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#define SYSTEM_ESR_EL3 0b1111001010010000
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#define ARMV8_MRS_DSPSR(Rt) (0xd53b4500 | (Rt))
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#define ARMV8_MSR_DSPSR(Rt) (0xd51b4500 | (Rt))
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#define ARMV8_MRS_DLR(Rt) (0xd53b4520 | (Rt))
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#define ARMV8_MSR_DLR(Rt) (0xd51b4520 | (Rt))
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/* T32 instruction to access coprocessor registers */
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#define ARMV8_MCR_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MCR(cp, opc1, Rt, CRn, CRm, opc2)
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#define ARMV8_MRC_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MRC(cp, opc1, Rt, CRn, CRm, opc2)
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/* T32 instructions to access DSPSR and DLR */
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#define ARMV8_MRC_DSPSR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, Rt)
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#define ARMV8_MCR_DSPSR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, Rt)
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#define ARMV8_MRC_DLR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 1, Rt)
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#define ARMV8_MCR_DLR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 1, Rt)
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#define ARMV8_DCPS1(IM) (0xd4a00001 | (((IM) & 0xFFFF) << 5))
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#define ARMV8_DCPS2(IM) (0xd4a00002 | (((IM) & 0xFFFF) << 5))
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#define ARMV8_DCPS3(IM) (0xd4a00003 | (((IM) & 0xFFFF) << 5))
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#define ARMV8_DCPS(EL, IM) (0xd4a00000 | (((IM) & 0xFFFF) << 5) | EL)
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#define ARMV8_DCPS_T1(EL) (0xf78f8000 | EL)
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#define ARMV8_DRPS 0xd6bf03e0
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#define ARMV8_ERET_T1 0xf3de8f00
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#define ARMV8_DSB_SY 0xd5033F9F
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#define ARMV8_DSB_SY_T1 0xf3bf8f4f
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#define ARMV8_ISB 0xd5033fdf
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#define ARMV8_ISB_SY_T1 0xf3bf8f6f
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#define ARMV8_MRS(System, Rt) (0xd5300000 | ((System) << 5) | (Rt))
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/* ARM V8 Move to system register. */
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#define ARMV8_MSR_GP(System, Rt) \
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(0xd5100000 | ((System) << 5) | (Rt))
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/* ARM V8 Move immediate to process state field. */
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#define ARMV8_MSR_IM(Op1, CRm, Op2) \
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(0xd500401f | ((Op1) << 16) | ((CRm) << 8) | ((Op2) << 5))
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#define ARMV8_MRS_T1(R, M1, Rd, M) (0xF3E08020 | (R << 20) | (M1 << 16) | (Rd << 8) | (M << 4))
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#define ARMV8_MRS_xPSR_T1(R, Rd) (0xF3EF8000 | (R << 20) | (Rd << 8))
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#define ARMV8_MSR_GP_T1(R, M1, Rd, M) (0xF3808020 | (R << 20) | (M1 << 8) | (Rd << 16) | (M << 4))
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#define ARMV8_MSR_GP_xPSR_T1(R, Rn, mask) (0xF3808000 | (R << 20) | (Rn << 16) | (mask << 8))
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#define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5))
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#define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5))
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#define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF))
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#define ARMV8_HLT_T1(Im) (0xba80 | (Im & 0x3f))
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#define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt))
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#define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F))
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#define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
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#define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
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#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd)
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#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
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#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
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#define ARMV8_LDRB_IP_T3(Rd, Rn) (0xf8100b01 | (Rn << 16) | (Rd << 12))
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#define ARMV8_LDRH_IP_T3(Rd, Rn) (0xf8300b02 | (Rn << 16) | (Rd << 12))
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#define ARMV8_LDRW_IP_T3(Rd, Rn) (0xf8500b04 | (Rn << 16) | (Rd << 12))
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#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
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#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
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#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
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#define ARMV8_STRB_IP_T3(Rd, Rn) (0xf8000b01 | (Rn << 16) | (Rd << 12))
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#define ARMV8_STRH_IP_T3(Rd, Rn) (0xf8200b02 | (Rn << 16) | (Rd << 12))
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#define ARMV8_STRW_IP_T3(Rd, Rn) (0xf8400b04 | (Rn << 16) | (Rd << 12))
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#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
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#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)
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#define ARMV8_MRS_FPCR(Rt) (0xd53b4400 | (Rt))
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#define ARMV8_MRS_FPSR(Rt) (0xd53b4420 | (Rt))
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#define ARMV8_MSR_FPCR(Rt) (0xd51b4400 | (Rt))
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#define ARMV8_MSR_FPSR(Rt) (0xd51b4420 | (Rt))
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#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
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enum armv8_opcode {
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READ_REG_CTR,
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READ_REG_CLIDR,
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READ_REG_CSSELR,
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READ_REG_CCSIDR,
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WRITE_REG_CSSELR,
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READ_REG_MPIDR,
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READ_REG_DTRRX,
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WRITE_REG_DTRTX,
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WRITE_REG_DSPSR,
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READ_REG_DSPSR,
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ARMV8_OPC_DSB_SY,
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ARMV8_OPC_DCPS,
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ARMV8_OPC_DRPS,
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ARMV8_OPC_ISB_SY,
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ARMV8_OPC_DCCISW,
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ARMV8_OPC_DCCIVAC,
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ARMV8_OPC_ICIVAU,
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ARMV8_OPC_HLT,
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ARMV8_OPC_STRB_IP,
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ARMV8_OPC_STRH_IP,
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ARMV8_OPC_STRW_IP,
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ARMV8_OPC_LDRB_IP,
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ARMV8_OPC_LDRH_IP,
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ARMV8_OPC_LDRW_IP,
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ARMV8_OPC_NUM,
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};
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extern uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode);
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extern void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64);
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#endif /* OPENOCD_TARGET_ARMV8_OPCODES_H */
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