b2821b6074
With this commit we add tcl configure files for ARCv2 HS Development kit(HSDK). HSDK board has Quad-core ARC HS38 CPU with L1 and L2 caches. Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5784 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
19 lines
415 B
INI
19 lines
415 B
INI
# Copyright (C) 2019, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)
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#
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source [find interface/ftdi/snps_sdp.cfg]
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adapter_khz 10000
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# ARCs supports only JTAG.
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transport select jtag
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# Configure SoC
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source [find target/snps_hsdk.cfg]
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