f5657aa76e
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. In the TCL scripts distributed with OpenOCD there are 1700+ lines that should be modified before switching to jimtcl 0.81. Apply the script below on every script in tcl folder. It fixes more than 92% of the lines %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- #!/usr/bin/perl -Wpi my $re_sym = qr{[a-z_][a-z0-9_]*}i; my $re_var = qr{(?:\$|\$::)$re_sym}; my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i; my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)}; my $re_op = qr{<<|>>|[+\-*/&|]}; my $re_expr = qr{( (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item) \s*$re_op\s* (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\)) )}x; # [expr [dict get $regsC100 SYM] + HEXNUM] s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/; # [ expr (EXPR) ] # [ expr EXPR ] # note: $re_expr captures '$3' s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/; s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/; %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6159 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
56 lines
1.4 KiB
Tcl
56 lines
1.4 KiB
Tcl
|
|
set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
|
|
set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
|
|
set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}]
|
|
set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}]
|
|
global RTTC_RTMR
|
|
global RTTC_RTAR
|
|
global RTTC_RTVR
|
|
global RTTC_RTSR
|
|
|
|
proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
|
|
set rtpres [expr {$VAL & 0x0ffff}]
|
|
global BIT16 BIT17
|
|
if { $rtpres == 0 } {
|
|
set rtpres 65536;
|
|
}
|
|
global AT91C_SLOWOSC_FREQ
|
|
# Nasty hack, make this a float by tacking a .0 on the end
|
|
# otherwise, jim makes the value an integer
|
|
set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0]
|
|
echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
|
|
if { $VAL & $BIT16 } {
|
|
echo "\tBit16 -> Alarm IRQ Enabled"
|
|
} else {
|
|
echo "\tBit16 -> Alarm IRQ Disabled"
|
|
}
|
|
if { $VAL & $BIT17 } {
|
|
echo "\tBit17 -> RTC Inc IRQ Enabled"
|
|
} else {
|
|
echo "\tBit17 -> RTC Inc IRQ Disabled"
|
|
}
|
|
# Bit 18 is write only.
|
|
}
|
|
|
|
proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
|
|
global BIT0 BIT1
|
|
if { $VAL & $BIT0 } {
|
|
echo "\tBit0 -> ALARM PENDING"
|
|
} else {
|
|
echo "\tBit0 -> alarm not pending"
|
|
}
|
|
if { $VAL & $BIT1 } {
|
|
echo "\tBit0 -> RTINC PENDING"
|
|
} else {
|
|
echo "\tBit0 -> rtinc not pending"
|
|
}
|
|
}
|
|
|
|
proc show_RTTC { } {
|
|
|
|
show_mmr32_reg RTTC_RTMR
|
|
show_mmr32_reg RTTC_RTAR
|
|
show_mmr32_reg RTTC_RTVR
|
|
show_mmr32_reg RTTC_RTSR
|
|
}
|