d2fb461621
The xilinx_ultrascale.cfg target is actually the configuration for a ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad core A53. Update the filename/comments to reflect this, and include the tap IDs for all known FPGA cores for this part. Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047 Signed-off-by: Jonathan McDowell <noodles@earth.li> Reviewed-on: http://openocd.zylin.com/4850 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
17 lines
346 B
INI
17 lines
346 B
INI
#
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# AVNET UltraZED EG StarterKit
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# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
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#
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source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
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# jtag transport only
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transport select jtag
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# reset lines are not wired
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reset_config none
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# slow default clock
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adapter_khz 1000
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set CHIPNAME uscale
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source [find target/xilinx_zynqmp.cfg]
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