170 lines
6.6 KiB
Plaintext
170 lines
6.6 KiB
Plaintext
/** @page primerjtag OpenOCD JTAG Primer
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JTAG is unnecessarily confusing, because JTAG is often confused with
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boundary scan, which is just one of its possible functions.
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JTAG is simply a communication interface designed to allow communication
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to functions contained on devices, for the designed purposes of
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initialisation, programming, testing, debugging, and anything else you
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want to use it for (as a chip designer).
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Think of JTAG as I2C for testing. It doesn't define what it can do,
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just a logical interface that allows a uniform channel for communication.
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See @par
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http://en.wikipedia.org/wiki/Joint_Test_Action_Group
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@image html jtag-state-machine-large.png
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The first page (among other things) shows a logical representation
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describing how multiple devices are wired up using JTAG. JTAG does not
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specify, data rates or interface levels (3.3V/1.8V, etc) each device can
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support different data rates/interface logic levels. How to wire them
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in a compatible way is an exercise for an engineer.
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Basically TMS controls which shift register is placed on the device,
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between TDI and TDO. The second diagram shows the state transitions on
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TMS which will select different shift registers.
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The first thing you need to do is reset the state machine, because when
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you connect to a chip you do not know what state the controller is in,you need
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to clock TMS as 1, at least 5 times. This will put you into "Test Logic
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Reset" State. Knowing this, you can, once reset, then track what each
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transition on TMS will do, and hence know what state the JTAG state
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machine is in.
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There are 2 "types" of shift registers. The Instruction shift register
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and the data shift register. The sizes of these are undefined, and can
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change from chip to chip. The Instruction register is used to select
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which Data register/data register function is used, and the data
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register is used to read data from that function or write data to it.
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Each of the states control what happens to either the data register or
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instruction register.
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For example, one of the data registers will be known as "bypass" this is
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(usually) a single bit which has no function and is used to bypass the
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chip. Assume we have 3 identical chips, wired up like the picture(wikipedia)
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and each has a 3 bits instruction register, and there are 2 known
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instructions (110 = bypass, 010 = "some other function") if we want to use
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"some other function", on the second chip in the line, and not change
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the other chips we would do the following transitions.
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From Test Logic Reset, TMS goes:
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0 1 1 0 0
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which puts every chip in the chain into the "Shift IR state"
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Then (while holding TMS as 0) TDI goes:
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0 1 1 0 1 0 0 1 1
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which puts the following values in the instruction shift register for
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each chip [110] [010] [110]
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The order is reversed, because we shift out the least significant bit
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first. Then we transition TMS:
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1 1 1 0 0
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which puts us in the "Shift DR state".
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Now when we clock data onto TDI (again while holding TMS to 0) , the
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data shifts through the data registers, and because of the instruction
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registers we selected ("some other function" has 8 bits in its data
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register), our total data register in the chain looks like this:
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0 00000000 0
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The first and last bit are in the "bypassed" chips, so values read from
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them are irrelevant and data written to them is ignored. But we need to
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write bits for those registers, because they are in the chain.
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If we wanted to write 0xF5 to the data register we would clock out of
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TDI (holding TMS to 0):
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0 1 0 1 0 1 1 1 1 0
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Again, we are clocking the least-significant bit first. Then we would
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clock TMS:
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1 1 0
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which updates the selected data register with the value 0xF5 and returns
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us to run test idle.
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If we needed to read the data register before over-writing it with F5,
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no sweat, that's already done, because the TDI/TDO are set up as a
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circular shift register, so if you write enough bits to fill the shift
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register, you will receive the "captured" contents of the data registers
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simultaneously on TDO.
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That's JTAG in a nutshell. On top of this, you need to get specs for
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target chips and work out what the various instruction registers/data
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registers do, so you can actually do something useful. That's where it
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gets interesting. But in and of itself, JTAG is actually very simple.
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@section primerjtagmore More Reading
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A separate primer contains information about @subpage primerjtagbs for
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developers that want to extend OpenOCD for such purposes.
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*/
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/** @page primerjtagbs JTAG Boundary Scan Primer
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The following page provides an introduction on JTAG that focuses on its
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boundary scan capabilities: @par
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http://www.engr.udayton.edu/faculty/jloomis/ece446/notes/jtag/jtag1.html
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OpenOCD does not presently have clear means of using JTAG for boundary
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scan testing purposes; however, some developers have explored the
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possibilities. The page contains information that may be useful to
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those wishing to implement boundary scan capabilities in OpenOCD.
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@section primerbsdl The BSDL Language
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For more information on the Boundary Scan Description Language (BSDL),
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the following page provides a good introduction: @par
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http://www.radio-electronics.com/info/t_and_m/boundaryscan/bsdl.php
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@section primerbsdlvendors Vendor BSDL Files
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NXP LPC: @par
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http://www.standardics.nxp.com/support/models/lpc2000/
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Freescale PowerPC: @par
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http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCBSDLFLS
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Freescale i.MX1 (too old): @par
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http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX1&nodeId=0162468rH311432973ZrDR&fpsp=1&tab=Design_Tools_Tab
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Renesas R32C/117: @par
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http://sg.renesas.com/fmwk.jsp?cnt=r32c116_7_8_root.jsp&fp=/products/mpumcu/m16c_family/r32c100_series/r32c116_7_8_group/
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- The device page does not come with BSDL file; you have to register to
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download them. @par
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http://www.corelis.com/support/BSDL.htm
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TI links theirs right off the generic page for each chip;
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this may be the case for other vendors as well. For example:
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- DaVinci DM355 -- http://www.ti.com/litv/zip/sprm262b
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- DaVinci DM6446
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- 2.1 silicon -- http://www.ti.com/litv/zip/sprm325a
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- older silicon -- http://www.ti.com/litv/zip/sprm203
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- OMAP 3530
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- CBB package -- http://www.ti.com/litv/zip/sprm315b
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- 515 ball s-PGBA, POP, 0.4mm pitch
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- CUS package -- http://www.ti.com/litv/zip/sprm314a
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- 515 ball s-PGBA, POP, 0.5mm pitch
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- CBC package -- http://www.ti.com/litv/zip/sprm346
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- 423 ball s-PGBA, 0.65mm pitch
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Many other files are available in the "Semiconductor Manufacturer's BSDL
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files" section of the following site: @par
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http://www.freelabs.com/~whitis/electronics/jtag/
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*/
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/** @file
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This file contains the @ref primerjtag and @ref primerjtagbs page.
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*/
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