1058 lines
29 KiB
C
1058 lines
29 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/***************************************************************************
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* STELLARIS is tested on LM3S811, LM3S6965
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "stellaris.h"
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#include "armv7m.h"
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#include "binarybuffer.h"
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#define DID0_VER(did0) ((did0>>28)&0x07)
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static int stellaris_register_commands(struct command_context_s *cmd_ctx);
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static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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static int stellaris_erase(struct flash_bank_s *bank, int first, int last);
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static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
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static int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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static int stellaris_auto_probe(struct flash_bank_s *bank);
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static int stellaris_probe(struct flash_bank_s *bank);
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static int stellaris_protect_check(struct flash_bank_s *bank);
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static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);
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static int stellaris_read_part_info(struct flash_bank_s *bank);
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static u32 stellaris_get_flash_status(flash_bank_t *bank);
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static void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
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//static u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
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static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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static int stellaris_mass_erase(struct flash_bank_s *bank);
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flash_driver_t stellaris_flash =
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{
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.name = "stellaris",
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.register_commands = stellaris_register_commands,
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.flash_bank_command = stellaris_flash_bank_command,
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.erase = stellaris_erase,
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.protect = stellaris_protect,
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.write = stellaris_write,
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.probe = stellaris_probe,
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.auto_probe = stellaris_auto_probe,
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.erase_check = default_flash_mem_blank_check,
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.protect_check = stellaris_protect_check,
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.info = stellaris_info
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};
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static struct {
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u32 partno;
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char *partname;
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} StellarisParts[] =
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{
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{0x01,"LM3S101"},
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{0x02,"LM3S102"},
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{0x03,"LM3S1625"},
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{0x04,"LM3S1626"},
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{0x05,"LM3S1627"},
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{0x06,"LM3S1607"},
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{0x10,"LM3S1776"},
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{0x19,"LM3S300"},
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{0x11,"LM3S301"},
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{0x12,"LM3S310"},
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{0x1A,"LM3S308"},
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{0x13,"LM3S315"},
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{0x14,"LM3S316"},
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{0x17,"LM3S317"},
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{0x18,"LM3S318"},
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{0x15,"LM3S328"},
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{0x2A,"LM3S600"},
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{0x21,"LM3S601"},
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{0x2B,"LM3S608"},
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{0x22,"LM3S610"},
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{0x23,"LM3S611"},
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{0x24,"LM3S612"},
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{0x25,"LM3S613"},
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{0x26,"LM3S615"},
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{0x28,"LM3S617"},
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{0x29,"LM3S618"},
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{0x27,"LM3S628"},
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{0x38,"LM3S800"},
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{0x31,"LM3S801"},
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{0x39,"LM3S808"},
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{0x32,"LM3S811"},
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{0x33,"LM3S812"},
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/*{0x33,"LM3S2616"},*/
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{0x34,"LM3S815"},
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{0x36,"LM3S817"},
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{0x37,"LM3S818"},
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{0x35,"LM3S828"},
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{0x39,"LM3S2276"},
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{0x3A,"LM3S2776"},
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{0x43,"LM3S3651"},
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{0x44,"LM3S3739"},
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{0x45,"LM3S3749"},
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{0x46,"LM3S3759"},
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{0x48,"LM3S3768"},
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{0x49,"LM3S3748"},
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{0x50,"LM3S2678"},
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{0x51,"LM3S2110"},
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{0x52,"LM3S2739"},
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{0x53,"LM3S2651"},
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{0x54,"LM3S2939"},
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{0x55,"LM3S2965"},
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{0x56,"LM3S2432"},
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{0x57,"LM3S2620"},
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{0x58,"LM3S2950"},
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{0x59,"LM3S2412"},
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{0x5A,"LM3S2533"},
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{0x61,"LM3S8630"},
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{0x62,"LM3S8970"},
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{0x63,"LM3S8730"},
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{0x64,"LM3S8530"},
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{0x65,"LM3S8930"},
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{0x71,"LM3S6610"},
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{0x72,"LM3S6950"},
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{0x73,"LM3S6965"},
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{0x74,"LM3S6110"},
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{0x75,"LM3S6432"},
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{0x76,"LM3S6537"},
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{0x77,"LM3S6753"},
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{0x78,"LM3S6952"},
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{0x80,"LM3S2671"},
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{0x81,"LM3S5632"},
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{0x82,"LM3S6422"},
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{0x83,"LM3S6633"},
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{0x84,"LM3S2139"},
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{0x85,"LM3S2637"},
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{0x86,"LM3S8738"},
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{0x88,"LM3S8938"},
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{0x89,"LM3S6938"},
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{0x8A,"LM3S5652"},
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{0x8B,"LM3S6637"},
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{0x8C,"LM3S8933"},
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{0x8D,"LM3S8733"},
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{0x8E,"LM3S8538"},
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{0x8F,"LM3S2948"},
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{0x91,"LM3S5662"},
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{0x96,"LM3S5732"},
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{0x97,"LM3S5737"},
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{0x99,"LM3S5747"},
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{0x9A,"LM3S5752"},
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{0x9B,"LM3S5757"},
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{0x9C,"LM3S5762"},
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{0x9D,"LM3S5767"},
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{0xA0,"LM3S5739"},
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{0xA1,"LM3S6100"},
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{0xA2,"LM3S2410"},
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{0xA3,"LM3S6730"},
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{0xA4,"LM3S2730"},
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{0xA5,"LM3S6420"},
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{0xA6,"LM3S8962"},
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{0xA7,"LM3S5749"},
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{0xA8,"LM3S5769"},
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{0xA9,"LM3S5768"},
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{0xB3,"LM3S1635"},
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{0xB4,"LM3S1850"},
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{0xB5,"LM3S1960"},
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{0xB7,"LM3S1937"},
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{0xB8,"LM3S1968"},
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{0xB9,"LM3S1751"},
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{0xBA,"LM3S1439"},
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{0xBB,"LM3S1512"},
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{0xBC,"LM3S1435"},
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{0xBD,"LM3S1637"},
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{0xBE,"LM3S1958"},
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{0xBF,"LM3S1110"},
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{0xC0,"LM3S1620"},
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{0xC1,"LM3S1150"},
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{0xC2,"LM3S1165"},
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{0xC3,"LM3S1133"},
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{0xC4,"LM3S1162"},
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{0xC5,"LM3S1138"},
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{0xC6,"LM3S1332"},
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{0xC7,"LM3S1538"},
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{0xD0,"LM3S6815"},
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{0xD1,"LM3S6816"},
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{0xD2,"LM3S6915"},
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{0xD3,"LM3S6916"},
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{0xD4,"LM3S2016"},
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{0xD5,"LM3S1615"},
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{0xD6,"LM3S1616"},
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{0xD7,"LM3S8971"},
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{0xD8,"LM3S1108"},
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{0xD9,"LM3S1101"},
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{0xDA,"LM3S1608"},
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{0xDB,"LM3S1601"},
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{0xDC,"LM3S1918"},
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{0xDD,"LM3S1911"},
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{0xDE,"LM3S2108"},
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{0xDF,"LM3S2101"},
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{0xE0,"LM3S2608"},
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{0xE1,"LM3S2601"},
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{0xE2,"LM3S2918"},
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{0xE3,"LM3S2911"},
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{0xE4,"LM3S6118"},
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{0xE5,"LM3S6111"},
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{0xE6,"LM3S6618"},
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{0xE7,"LM3S6611"},
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{0xE8,"LM3S6918"},
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{0xE9,"LM3S6911"},
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{0,"Unknown part"}
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};
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static char * StellarisClassname[5] =
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{
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"Sandstorm",
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"Fury",
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"Unknown",
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"DustDevil",
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"Tempest"
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};
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/***************************************************************************
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* openocd command interface *
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***************************************************************************/
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/* flash_bank stellaris <base> <size> 0 0 <target#>
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*/
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static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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{
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stellaris_flash_bank_t *stellaris_info;
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if (argc < 6)
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{
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LOG_WARNING("incomplete flash_bank stellaris configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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stellaris_info = calloc(sizeof(stellaris_flash_bank_t), 1);
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bank->base = 0x0;
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bank->driver_priv = stellaris_info;
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stellaris_info->target_name = "Unknown target";
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/* part wasn't probed for info yet */
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stellaris_info->did1 = 0;
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/* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
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return ERROR_OK;
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}
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static int stellaris_register_commands(struct command_context_s *cmd_ctx)
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{
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command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, "stellaris flash specific commands");
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register_command(cmd_ctx, stm32x_cmd, "mass_erase", stellaris_handle_mass_erase_command, COMMAND_EXEC, "mass erase device");
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return ERROR_OK;
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}
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static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
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{
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int printed, device_class;
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stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
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stellaris_read_part_info(bank);
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if (stellaris_info->did1 == 0)
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{
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printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n");
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buf += printed;
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buf_size -= printed;
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (DID0_VER(stellaris_info->did0) > 0)
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{
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device_class = (stellaris_info->did0>>16) & 0xFF;
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}
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else
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{
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device_class = 0;
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}
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printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
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device_class, StellarisClassname[device_class], stellaris_info->target_name,
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'A' + ((stellaris_info->did0>>8) & 0xFF), (stellaris_info->did0) & 0xFF);
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buf += printed;
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buf_size -= printed;
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printed = snprintf(buf, buf_size, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik, flashsize: %ik\n",
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stellaris_info->did1, stellaris_info->did1, "ARMV7M", (1+((stellaris_info->dc0>>16) & 0xFFFF))/4, (1+(stellaris_info->dc0 & 0xFFFF))*2);
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buf += printed;
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buf_size -= printed;
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printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz, rcc is 0x%x \n", stellaris_info->mck_freq / 1000, stellaris_info->rcc);
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buf += printed;
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buf_size -= printed;
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if (stellaris_info->num_lockbits>0)
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{
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printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", stellaris_info->pagesize, stellaris_info->num_lockbits, stellaris_info->lockbits,stellaris_info->num_pages/stellaris_info->num_lockbits);
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buf += printed;
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buf_size -= printed;
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}
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return ERROR_OK;
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}
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/***************************************************************************
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* chip identification and status *
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***************************************************************************/
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static u32 stellaris_get_flash_status(flash_bank_t *bank)
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{
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target_t *target = bank->target;
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u32 fmc;
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target_read_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, &fmc);
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return fmc;
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}
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/** Read clock configuration and set stellaris_info->usec_clocks*/
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static void stellaris_read_clock_info(flash_bank_t *bank)
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{
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stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
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target_t *target = bank->target;
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u32 rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
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unsigned long mainfreq;
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target_read_u32(target, SCB_BASE|RCC, &rcc);
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LOG_DEBUG("Stellaris RCC %x", rcc);
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target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);
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LOG_DEBUG("Stellaris PLLCFG %x", pllcfg);
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stellaris_info->rcc = rcc;
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sysdiv = (rcc>>23) & 0xF;
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usesysdiv = (rcc>>22) & 0x1;
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bypass = (rcc>>11) & 0x1;
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oscsrc = (rcc>>4) & 0x3;
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/* xtal = (rcc>>6)&0xF; */
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switch (oscsrc)
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{
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case 0:
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mainfreq = 6000000; /* Default xtal */
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break;
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case 1:
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mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */
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break;
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case 2:
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mainfreq = 5625000; /* Internal osc. / 4 */
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break;
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case 3:
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LOG_WARNING("Invalid oscsrc (3) in rcc register");
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mainfreq = 6000000;
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break;
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default: /* NOTREACHED */
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mainfreq = 0;
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break;
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}
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if (!bypass)
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mainfreq = 200000000; /* PLL out frec */
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if (usesysdiv)
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stellaris_info->mck_freq = mainfreq/(1+sysdiv);
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else
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stellaris_info->mck_freq = mainfreq;
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/* Forget old flash timing */
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stellaris_set_flash_mode(bank, 0);
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}
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/* Setup the timimg registers */
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static void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
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{
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stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
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target_t *target = bank->target;
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u32 usecrl = (stellaris_info->mck_freq/1000000ul-1);
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LOG_DEBUG("usecrl = %i",usecrl);
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target_write_u32(target, SCB_BASE|USECRL, usecrl);
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}
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#if 0
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static u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
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{
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u32 status;
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/* Stellaris waits for cmdbit to clear */
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while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
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{
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LOG_DEBUG("status: 0x%x", status);
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alive_sleep(1);
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}
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/* Flash errors are reflected in the FLASH_CRIS register */
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return status;
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}
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/* Send one command to the flash controller */
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static int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
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{
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u32 fmc;
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target_t *target = bank->target;
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fmc = FMC_WRKEY | cmd;
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target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);
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LOG_DEBUG("Flash command: 0x%x", fmc);
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if (stellaris_wait_status_busy(bank, cmd, 100))
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{
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return ERROR_FLASH_OPERATION_FAILED;
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}
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return ERROR_OK;
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}
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#endif
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/* Read device id register, main clock frequency register and fill in driver info structure */
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static int stellaris_read_part_info(struct flash_bank_s *bank)
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{
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stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
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target_t *target = bank->target;
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u32 did0, did1, ver, fam, status;
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int i;
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/* Read and parse chip identification register */
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target_read_u32(target, SCB_BASE|DID0, &did0);
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target_read_u32(target, SCB_BASE|DID1, &did1);
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target_read_u32(target, SCB_BASE|DC0, &stellaris_info->dc0);
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target_read_u32(target, SCB_BASE|DC1, &stellaris_info->dc1);
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LOG_DEBUG("did0 0x%x, did1 0x%x, dc0 0x%x, dc1 0x%x", did0, did1, stellaris_info->dc0, stellaris_info->dc1);
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ver = did0 >> 28;
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if((ver != 0) && (ver != 1))
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{
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LOG_WARNING("Unknown did0 version, cannot identify target");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (did1 == 0)
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{
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LOG_WARNING("Cannot identify target as a Stellaris");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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|
|
ver = did1 >> 28;
|
|
fam = (did1 >> 24) & 0xF;
|
|
if(((ver != 0) && (ver != 1)) || (fam != 0))
|
|
{
|
|
LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
|
|
}
|
|
|
|
for (i = 0; StellarisParts[i].partno; i++)
|
|
{
|
|
if (StellarisParts[i].partno == ((did1 >> 16) & 0xFF))
|
|
break;
|
|
}
|
|
|
|
stellaris_info->target_name = StellarisParts[i].partname;
|
|
|
|
stellaris_info->did0 = did0;
|
|
stellaris_info->did1 = did1;
|
|
|
|
stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
|
|
stellaris_info->num_pages = 2 *(1+(stellaris_info->dc0 & 0xFFFF));
|
|
stellaris_info->pagesize = 1024;
|
|
bank->size = 1024 * stellaris_info->num_pages;
|
|
stellaris_info->pages_in_lockregion = 2;
|
|
target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
|
|
|
|
/* provide this for the benefit of the higher flash driver layers */
|
|
bank->num_sectors = stellaris_info->num_pages;
|
|
bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
|
|
for (i = 0; i < bank->num_sectors; i++)
|
|
{
|
|
bank->sectors[i].offset = i * stellaris_info->pagesize;
|
|
bank->sectors[i].size = stellaris_info->pagesize;
|
|
bank->sectors[i].is_erased = -1;
|
|
bank->sectors[i].is_protected = -1;
|
|
}
|
|
|
|
/* Read main and master clock freqency register */
|
|
stellaris_read_clock_info(bank);
|
|
|
|
status = stellaris_get_flash_status(bank);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/***************************************************************************
|
|
* flash operations *
|
|
***************************************************************************/
|
|
|
|
static int stellaris_protect_check(struct flash_bank_s *bank)
|
|
{
|
|
u32 status;
|
|
|
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
stellaris_read_part_info(bank);
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
LOG_WARNING("Cannot identify target as an AT91SAM");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
status = stellaris_get_flash_status(bank);
|
|
stellaris_info->lockbits = status >> 16;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stellaris_erase(struct flash_bank_s *bank, int first, int last)
|
|
{
|
|
int banknr;
|
|
u32 flash_fmc, flash_cris;
|
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
|
target_t *target = bank->target;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
stellaris_read_part_info(bank);
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
LOG_WARNING("Cannot identify target as Stellaris");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages))
|
|
{
|
|
return ERROR_FLASH_SECTOR_INVALID;
|
|
}
|
|
|
|
if ((first == 0) && (last == ((int)stellaris_info->num_pages-1)))
|
|
{
|
|
return stellaris_mass_erase(bank);
|
|
}
|
|
|
|
/* Configure the flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_mode(bank,0);
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
|
|
|
|
for (banknr = first; banknr <= last; banknr++)
|
|
{
|
|
/* Address is first word in page */
|
|
target_write_u32(target, FLASH_FMA, banknr * stellaris_info->pagesize);
|
|
/* Write erase command */
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while(flash_fmc & FMC_ERASE);
|
|
|
|
/* Check acess violations */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
if(flash_cris & (AMASK))
|
|
{
|
|
LOG_WARNING("Error erasing flash page %i, flash_cris 0x%x", banknr, flash_cris);
|
|
target_write_u32(target, FLASH_CRIS, 0);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
bank->sectors[banknr].is_erased = 1;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)
|
|
{
|
|
u32 fmppe, flash_fmc, flash_cris;
|
|
int lockregion;
|
|
|
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
|
target_t *target = bank->target;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))
|
|
{
|
|
return ERROR_FLASH_SECTOR_INVALID;
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
stellaris_read_part_info(bank);
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
LOG_WARNING("Cannot identify target as an Stellaris MCU");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
/* Configure the flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_mode(bank, 0);
|
|
|
|
fmppe = stellaris_info->lockbits;
|
|
for (lockregion = first; lockregion <= last; lockregion++)
|
|
{
|
|
if (set)
|
|
fmppe &= ~(1<<lockregion);
|
|
else
|
|
fmppe |= (1<<lockregion);
|
|
}
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
|
|
|
|
LOG_DEBUG("fmppe 0x%x",fmppe);
|
|
target_write_u32(target, SCB_BASE|FMPPE, fmppe);
|
|
/* Commit FMPPE */
|
|
target_write_u32(target, FLASH_FMA, 1);
|
|
/* Write commit command */
|
|
/* TODO safety check, sice this cannot be undone */
|
|
LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
|
|
/* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while(flash_fmc & FMC_COMT);
|
|
|
|
/* Check acess violations */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
if(flash_cris & (AMASK))
|
|
{
|
|
LOG_WARNING("Error setting flash page protection, flash_cris 0x%x", flash_cris);
|
|
target_write_u32(target, FLASH_CRIS, 0);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static u8 stellaris_write_code[] =
|
|
{
|
|
/*
|
|
Call with :
|
|
r0 = buffer address
|
|
r1 = destination address
|
|
r2 = bytecount (in) - endaddr (work)
|
|
|
|
Used registers:
|
|
r3 = pFLASH_CTRL_BASE
|
|
r4 = FLASHWRITECMD
|
|
r5 = #1
|
|
r6 = bytes written
|
|
r7 = temp reg
|
|
*/
|
|
0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
|
|
0x08,0x4C, /* ldr r4,FLASHWRITECMD */
|
|
0x01,0x25, /* movs r5, 1 */
|
|
0x00,0x26, /* movs r6, #0 */
|
|
/* mainloop: */
|
|
0x19,0x60, /* str r1, [r3, #0] */
|
|
0x87,0x59, /* ldr r7, [r0, r6] */
|
|
0x5F,0x60, /* str r7, [r3, #4] */
|
|
0x9C,0x60, /* str r4, [r3, #8] */
|
|
/* waitloop: */
|
|
0x9F,0x68, /* ldr r7, [r3, #8] */
|
|
0x2F,0x42, /* tst r7, r5 */
|
|
0xFC,0xD1, /* bne waitloop */
|
|
0x04,0x31, /* adds r1, r1, #4 */
|
|
0x04,0x36, /* adds r6, r6, #4 */
|
|
0x96,0x42, /* cmp r6, r2 */
|
|
0xF4,0xD1, /* bne mainloop */
|
|
/* exit: */
|
|
0xFE,0xE7, /* b exit */
|
|
/* pFLASH_CTRL_BASE: */
|
|
0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
|
|
/* FLASHWRITECMD: */
|
|
0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
|
|
};
|
|
|
|
static int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)
|
|
{
|
|
target_t *target = bank->target;
|
|
u32 buffer_size = 8192;
|
|
working_area_t *source;
|
|
working_area_t *write_algorithm;
|
|
u32 address = bank->base + offset;
|
|
reg_param_t reg_params[3];
|
|
armv7m_algorithm_t armv7m_info;
|
|
int retval = ERROR_OK;
|
|
|
|
LOG_DEBUG("(bank=%p buffer=%p offset=%08X wcount=%08X)",
|
|
bank, buffer, offset, wcount);
|
|
|
|
/* flash write code */
|
|
if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
|
|
{
|
|
LOG_WARNING("no working area available, can't do block memory writes");
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
};
|
|
|
|
target_write_buffer(target, write_algorithm->address, sizeof(stellaris_write_code), stellaris_write_code);
|
|
|
|
/* memory buffer */
|
|
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
|
|
{
|
|
LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08X source=%p)",
|
|
target, buffer_size, source);
|
|
buffer_size /= 2;
|
|
if (buffer_size <= 256)
|
|
{
|
|
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
|
|
if (write_algorithm)
|
|
target_free_working_area(target, write_algorithm);
|
|
|
|
LOG_WARNING("no large enough working area available, can't do block memory writes");
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
}
|
|
};
|
|
|
|
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
|
|
armv7m_info.core_mode = ARMV7M_MODE_ANY;
|
|
|
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
|
|
|
while (wcount > 0)
|
|
{
|
|
u32 thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
|
|
|
|
target_write_buffer(target, source->address, thisrun_count * 4, buffer);
|
|
|
|
buf_set_u32(reg_params[0].value, 0, 32, source->address);
|
|
buf_set_u32(reg_params[1].value, 0, 32, address);
|
|
buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
|
|
LOG_INFO("Algorithm flash write %i words to 0x%x, %i remaining", thisrun_count, address, wcount);
|
|
LOG_DEBUG("Algorithm flash write %i words to 0x%x, %i remaining", thisrun_count, address, wcount);
|
|
if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
|
|
{
|
|
LOG_ERROR("error executing stellaris flash write algorithm");
|
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
|
break;
|
|
}
|
|
|
|
buffer += thisrun_count * 4;
|
|
address += thisrun_count * 4;
|
|
wcount -= thisrun_count;
|
|
}
|
|
|
|
target_free_working_area(target, write_algorithm);
|
|
target_free_working_area(target, source);
|
|
|
|
destroy_reg_param(®_params[0]);
|
|
destroy_reg_param(®_params[1]);
|
|
destroy_reg_param(®_params[2]);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
|
{
|
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
|
target_t *target = bank->target;
|
|
u32 address = offset;
|
|
u32 flash_cris, flash_fmc;
|
|
u32 words_remaining = (count / 4);
|
|
u32 bytes_remaining = (count & 0x00000003);
|
|
u32 bytes_written = 0;
|
|
int retval;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
LOG_DEBUG("(bank=%p buffer=%p offset=%08X count=%08X)",
|
|
bank, buffer, offset, count);
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
stellaris_read_part_info(bank);
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
LOG_WARNING("Cannot identify target as a Stellaris processor");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
if (offset & 0x3)
|
|
{
|
|
LOG_WARNING("offset size must be word aligned");
|
|
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
|
|
}
|
|
|
|
if (offset + count > bank->size)
|
|
return ERROR_FLASH_DST_OUT_OF_BANK;
|
|
|
|
/* Configure the flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_mode(bank, 0);
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
|
|
|
|
/* multiple words to be programmed? */
|
|
if (words_remaining > 0)
|
|
{
|
|
/* try using a block write */
|
|
if ((retval = stellaris_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
|
|
{
|
|
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
|
|
{
|
|
/* if block write failed (no sufficient working area),
|
|
* we use normal (slow) single dword accesses */
|
|
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
|
}
|
|
else if (retval == ERROR_FLASH_OPERATION_FAILED)
|
|
{
|
|
/* if an error occured, we examine the reason, and quit */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
|
|
LOG_ERROR("flash writing failed with CRIS: 0x%x", flash_cris);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
buffer += words_remaining * 4;
|
|
address += words_remaining * 4;
|
|
words_remaining = 0;
|
|
}
|
|
}
|
|
|
|
while (words_remaining > 0)
|
|
{
|
|
if (!(address & 0xff))
|
|
LOG_DEBUG("0x%x", address);
|
|
|
|
/* Program one word */
|
|
target_write_u32(target, FLASH_FMA, address);
|
|
target_write_buffer(target, FLASH_FMD, 4, buffer);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
|
|
/* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
|
|
/* Wait until write complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
} while (flash_fmc & FMC_WRITE);
|
|
|
|
buffer += 4;
|
|
address += 4;
|
|
words_remaining--;
|
|
}
|
|
|
|
if (bytes_remaining)
|
|
{
|
|
u8 last_word[4] = {0xff, 0xff, 0xff, 0xff};
|
|
int i = 0;
|
|
|
|
while(bytes_remaining > 0)
|
|
{
|
|
last_word[i++] = *(buffer + bytes_written);
|
|
bytes_remaining--;
|
|
bytes_written++;
|
|
}
|
|
|
|
if (!(address & 0xff))
|
|
LOG_DEBUG("0x%x", address);
|
|
|
|
/* Program one word */
|
|
target_write_u32(target, FLASH_FMA, address);
|
|
target_write_buffer(target, FLASH_FMD, 4, last_word);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
|
|
/* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
|
|
/* Wait until write complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
} while (flash_fmc & FMC_WRITE);
|
|
}
|
|
|
|
/* Check access violations */
|
|
target_read_u32(target, FLASH_CRIS, &flash_cris);
|
|
if (flash_cris & (AMASK))
|
|
{
|
|
LOG_DEBUG("flash_cris 0x%x", flash_cris);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stellaris_probe(struct flash_bank_s *bank)
|
|
{
|
|
/* we can't probe on an stellaris
|
|
* if this is an stellaris, it has the configured flash
|
|
*/
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
/* stellaris_read_part_info() already takes care about error checking and reporting */
|
|
return stellaris_read_part_info(bank);
|
|
}
|
|
|
|
static int stellaris_auto_probe(struct flash_bank_s *bank)
|
|
{
|
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
|
if (stellaris_info->did1)
|
|
return ERROR_OK;
|
|
return stellaris_probe(bank);
|
|
}
|
|
|
|
static int stellaris_mass_erase(struct flash_bank_s *bank)
|
|
{
|
|
target_t *target = NULL;
|
|
stellaris_flash_bank_t *stellaris_info = NULL;
|
|
u32 flash_fmc;
|
|
|
|
stellaris_info = bank->driver_priv;
|
|
target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
stellaris_read_part_info(bank);
|
|
}
|
|
|
|
if (stellaris_info->did1 == 0)
|
|
{
|
|
LOG_WARNING("Cannot identify target as Stellaris");
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
/* Configure the flash controller timing */
|
|
stellaris_read_clock_info(bank);
|
|
stellaris_set_flash_mode(bank, 0);
|
|
|
|
/* Clear and disable flash programming interrupts */
|
|
target_write_u32(target, FLASH_CIM, 0);
|
|
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
|
|
|
|
target_write_u32(target, FLASH_FMA, 0);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while (flash_fmc & FMC_MERASE);
|
|
|
|
/* if device has > 128k, then second erase cycle is needed
|
|
* this is only valid for older devices, but will not hurt */
|
|
if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
|
|
{
|
|
target_write_u32(target, FLASH_FMA, 0x20000);
|
|
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
|
|
/* Wait until erase complete */
|
|
do
|
|
{
|
|
target_read_u32(target, FLASH_FMC, &flash_fmc);
|
|
}
|
|
while (flash_fmc & FMC_MERASE);
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
|
{
|
|
flash_bank_t *bank;
|
|
int i;
|
|
|
|
if (argc < 1)
|
|
{
|
|
command_print(cmd_ctx, "stellaris mass_erase <bank>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
|
|
if (!bank)
|
|
{
|
|
command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
|
|
return ERROR_OK;
|
|
}
|
|
|
|
if (stellaris_mass_erase(bank) == ERROR_OK)
|
|
{
|
|
/* set all sectors as erased */
|
|
for (i = 0; i < bank->num_sectors; i++)
|
|
{
|
|
bank->sectors[i].is_erased = 1;
|
|
}
|
|
|
|
command_print(cmd_ctx, "stellaris mass erase complete");
|
|
}
|
|
else
|
|
{
|
|
command_print(cmd_ctx, "stellaris mass erase failed");
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|