da41bce3ae
With this patch we introduce set/unset breakpoints routines and add/remove bp handlers. Currently soft breakpoints are only supported. Changes since v1: * Change if-statement in arc_remove_breakpoint * Squash changes from http://openocd.zylin.com/#/c/5641/ in this commit to fix build. Change-Id: Ib10ccdb02fd1606e4f407f012b1bee106a8ffccd Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5641 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
251 lines
7.1 KiB
C
251 lines
7.1 KiB
C
/***************************************************************************
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* Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
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* Frank Dols <frank.dols@synopsys.com> *
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* Mischa Jonker <mischa.jonker@synopsys.com> *
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* Anton Kolesov <anton.kolesov@synopsys.com> *
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* Evgeniy Didin <didin@synopsys.com> *
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* *
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* SPDX-License-Identifier: GPL-2.0-or-later *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARC_H
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#define OPENOCD_TARGET_ARC_H
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#include <helper/time_support.h>
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#include <jtag/jtag.h>
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#include "algorithm.h"
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#include "breakpoints.h"
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#include "jtag/interface.h"
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#include "register.h"
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#include "target.h"
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#include "target_request.h"
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#include "target_type.h"
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#include "helper/bits.h"
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#include "arc_jtag.h"
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#include "arc_cmd.h"
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#include "arc_mem.h"
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#define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */
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#define AUX_DEBUG_REG 0x5
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#define AUX_PC_REG 0x6
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#define AUX_STATUS32_REG 0xA
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#define SET_CORE_FORCE_HALT BIT(1)
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#define SET_CORE_HALT_BIT BIT(0) /* STATUS32[0] = H field */
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#define SET_CORE_ENABLE_INTERRUPTS BIT(31)
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/* STATUS32[5] or AE bit indicates if the processor is in exception state */
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#define SET_CORE_AE_BIT BIT(5)
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/* Single instruction step bit in Debug register */
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#define SET_CORE_SINGLE_INSTR_STEP BIT(11)
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#define AUX_STATUS32_REG_HALT_BIT BIT(0)
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#define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */
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/* Reserved core registers */
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#define CORE_R61_NUM (61)
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#define CORE_R62_NUM (62)
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#define CORE_REG_MAX_NUMBER (63)
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/* Limit reg_type/reg_type_field name to 20 symbols */
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#define REG_TYPE_MAX_NAME_LENGTH 20
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/* ARC 32bits opcodes */
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#define ARC_SDBBP_32 0x256F003F /* BRK */
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/* ARC 16bits opcodes */
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#define ARC_SDBBP_16 0x7FFF /* BRK_S */
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struct arc_reg_bitfield {
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struct reg_data_type_bitfield bitfield;
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char name[REG_TYPE_MAX_NAME_LENGTH];
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};
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/* Register data type */
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struct arc_reg_data_type {
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struct list_head list;
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struct reg_data_type data_type;
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struct reg_data_type_flags data_type_flags;
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struct reg_data_type_struct data_type_struct;
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char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
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struct arc_reg_bitfield *bitfields;
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union {
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struct reg_data_type_struct_field *reg_type_struct_field;
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struct reg_data_type_flags_field *reg_type_flags_field;
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};
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};
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/* Standard GDB register types */
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static const struct reg_data_type standard_gdb_types[] = {
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{ .type = REG_TYPE_INT, .id = "int" },
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{ .type = REG_TYPE_INT8, .id = "int8" },
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{ .type = REG_TYPE_INT16, .id = "int16" },
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{ .type = REG_TYPE_INT32, .id = "int32" },
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{ .type = REG_TYPE_INT64, .id = "int64" },
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{ .type = REG_TYPE_INT128, .id = "int128" },
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{ .type = REG_TYPE_UINT8, .id = "uint8" },
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{ .type = REG_TYPE_UINT16, .id = "uint16" },
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{ .type = REG_TYPE_UINT32, .id = "uint32" },
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{ .type = REG_TYPE_UINT64, .id = "uint64" },
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{ .type = REG_TYPE_UINT128, .id = "uint128" },
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{ .type = REG_TYPE_CODE_PTR, .id = "code_ptr" },
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{ .type = REG_TYPE_DATA_PTR, .id = "data_ptr" },
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{ .type = REG_TYPE_FLOAT, .id = "float" },
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{ .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
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{ .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
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};
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struct arc_common {
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uint32_t common_magic;
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struct arc_jtag jtag_info;
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struct reg_cache *core_and_aux_cache;
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struct reg_cache *bcr_cache;
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/* Indicate if cach was built (for deinit function) */
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bool core_aux_cache_built;
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bool bcr_cache_built;
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/* Closely Coupled memory(CCM) regions for performance-critical
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* code (optional). */
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uint32_t iccm0_start;
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uint32_t iccm0_end;
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uint32_t iccm1_start;
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uint32_t iccm1_end;
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uint32_t dccm_start;
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uint32_t dccm_end;
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int irq_state;
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/* Register descriptions */
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struct list_head reg_data_types;
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struct list_head core_reg_descriptions;
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struct list_head aux_reg_descriptions;
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struct list_head bcr_reg_descriptions;
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unsigned long num_regs;
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unsigned long num_core_regs;
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unsigned long num_aux_regs;
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unsigned long num_bcr_regs;
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unsigned long last_general_reg;
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/* PC register location in register cache. */
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unsigned long pc_index_in_cache;
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/* DEBUG register location in register cache. */
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unsigned long debug_index_in_cache;
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};
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/* Borrowed from nds32.h */
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#define CHECK_RETVAL(action) \
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do { \
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int __retval = (action); \
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if (__retval != ERROR_OK) { \
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LOG_DEBUG("error while calling \"%s\"", \
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# action); \
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return __retval; \
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} \
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} while (0)
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#define JIM_CHECK_RETVAL(action) \
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do { \
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int __retval = (action); \
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if (__retval != JIM_OK) { \
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LOG_DEBUG("error while calling \"%s\"", \
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# action); \
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return __retval; \
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} \
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} while (0)
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static inline struct arc_common *target_to_arc(struct target *target)
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{
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return target->arch_info;
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}
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/* ----- Inlined functions ------------------------------------------------- */
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/**
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* Convert data in host endianness to the middle endian. This is required to
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* write 4-byte instructions.
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*/
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static inline void arc_h_u32_to_me(uint8_t *buf, int val)
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{
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buf[1] = (uint8_t) (val >> 24);
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buf[0] = (uint8_t) (val >> 16);
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buf[3] = (uint8_t) (val >> 8);
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buf[2] = (uint8_t) (val >> 0);
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}
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/**
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* Convert data in middle endian to host endian. This is required to read 32-bit
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* instruction from little endian ARCs.
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*/
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static inline uint32_t arc_me_to_h_u32(const uint8_t *buf)
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{
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return (uint32_t)(buf[2] | buf[3] << 8 | buf[0] << 16 | buf[1] << 24);
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}
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/* ARC Register description */
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struct arc_reg_desc {
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struct target *target;
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/* Register name */
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char *name;
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/* Actual place of storing reg_value */
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uint8_t reg_value[4];
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/* Actual place of storing register feature */
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struct reg_feature feature;
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/* GDB XML feature */
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char *gdb_xml_feature;
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/* Is this a register in g/G-packet? */
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bool is_general;
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/* Architectural number: core reg num or AUX reg num */
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uint32_t arch_num;
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/* Core or AUX register? */
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bool is_core;
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/* Build configuration register? */
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bool is_bcr;
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/* Data type */
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struct reg_data_type *data_type;
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struct list_head list;
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};
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/* Error codes */
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#define ERROR_ARC_REGISTER_NOT_FOUND (-700)
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#define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
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#define ERROR_ARC_REGISTER_IS_NOT_STRUCT (-702)
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#define ERROR_ARC_FIELD_IS_NOT_BITFIELD (-703)
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#define ERROR_ARC_REGTYPE_NOT_FOUND (-704)
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void free_reg_desc(struct arc_reg_desc *r);
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void arc_reg_data_type_add(struct target *target,
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struct arc_reg_data_type *data_type);
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int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
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const char * const type_name, const size_t type_name_len);
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struct reg *arc_reg_get_by_name(struct reg_cache *first,
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const char *name, bool search_all);
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int arc_reg_get_field(struct target *target, const char *reg_name,
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const char *field_name, uint32_t *value_ptr);
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#endif /* OPENOCD_TARGET_ARC_H */
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