5df5e89cf3
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.
This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command:
find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types TRAILING_WHITESPACE --fix-inplace -f {} \;
The patch only changes amount and position of whitespace, thus
the following commands show empty diff
git diff -w
git log -w -p
git log -w --stat
Change-Id: Ie7e3a236f4db9c70019e3b3c7e851edbd3a9dd84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5616
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
89 lines
2.0 KiB
INI
89 lines
2.0 KiB
INI
source [find target/lpc3250.cfg]
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adapter srst delay 200
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jtag_ntrst_delay 1
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adapter speed 200
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reset_config trst_and_srst separate
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arm7_9 dcc_downloads enable
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-start {
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arm7_9 fast_memory_access disable
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adapter speed 200
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}
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$_TARGETNAME configure -event reset-end {
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adapter speed 6000
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arm7_9 fast_memory_access enable
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}
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$_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
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# Bare-bones initialization of core clocks and SDRAM
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proc phytec_lpc3250_init { } {
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# Set clock dividers
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# ARMCLK = 266.5 MHz
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# HCLK = 133.25 MHz
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# PERIPHCLK = 13.325 MHz
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mww 0x400040BC 0
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mww 0x40004050 0x140
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mww 0x40004040 0x4D
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mww 0x40004058 0x16250
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# Init PLLs
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mww 0x40004044 0x006
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sleep 1 busy
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mww 0x40004044 0x106
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sleep 1 busy
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mww 0x40004044 0x006
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sleep 1 busy
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mww 0x40004048 0x2
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# Init SDRAM with 133 MHz timings
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mww 0x40028134 0x00FFFFFF
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mww 0x4002802C 0x00000008
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mww 0x31080000 1
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mww 0x31080008 0
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mww 0x40004068 0x1C000
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mww 0x31080028 0x11
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mww 0x31080400 0
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mww 0x31080440 0
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mww 0x31080460 0
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mww 0x31080480 0
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# Delays
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mww 0x31080030 1
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mww 0x31080034 6
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mww 0x31080038 10
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mww 0x31080044 1
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mww 0x31080048 9
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mww 0x3108004C 12
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mww 0x31080050 10
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mww 0x31080054 1
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mww 0x31080058 1
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mww 0x3108005C 0
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mww 0x31080100 0x5680
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mww 0x31080104 0x302
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# Init sequence
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mww 0x31080020 0x193
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sleep 1 busy
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mww 0x31080024 1
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mww 0x31080020 0x113
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sleep 1 busy
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mww 0x31080020 0x013
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sleep 1 busy
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mww 0x31080024 65
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mww 0x31080020 0x093
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mdw 0x80020000
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mww 0x31080020 0x013
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# SYS_CTRL remapping
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mww 0x40004014 1
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}
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