openocd/tcl/target/ti_tms570.cfg
Seth LaForge 3427cf2b7e cortex_a: fix endiannes issues on TI TMS570
The TI TMS470 and TMS570 series of processors are BE-32 processors,
despite BE-32 not being supported by ARM in the Cortex-R4 core. TI
hacked in BE-32 support, which requires odd swizzling in OpenOCD to
make memory reads and writes function correctly. In particular,
without this change, OpenOCD word reads and writes had the bytes
reversed, and halfword and byte packed reads were reading garbage.
In my testing, this change fixes these problems.

Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/2064
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-04-14 18:20:36 +00:00

57 lines
1.4 KiB
INI

adapter_khz 1500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME tms570
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN big
}
# TMS570 has an ICEpick-C on which we need the router commands.
source [find target/icepick.cfg]
# Main DAP
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x0B8A002F
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
# ICEpick-C (JTAG route controller)
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0B8A002F
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID -ignore-version
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
# Cortex R4 target
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
# TMS570 uses quirky BE-32 mode
$_TARGETNAME dap ti_be_32_quirks 1
$_TARGETNAME configure -event gdb-attach {
cortex_r4 dbginit
halt
}
$_TARGETNAME configure -event "reset-assert" {
global _CHIPNAME
# assert warm system reset through ICEPick
icepick_c_wreset $_CHIPNAME.jrc
}