218a4b4e20
ST-AN was mentioned but there was no reference Change-Id: Ie065f8faba94d63cf391a994ec895692d499394e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/224 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
26 lines
1.0 KiB
INI
26 lines
1.0 KiB
INI
# Configuration for the ST SPEAr310 Evaluation board
|
|
# EVALSPEAr310 Rev. 2.0, modified to enable SRST on JTAG connector
|
|
# http://www.st.com/spear
|
|
#
|
|
# List of board modifications to enable SRST, as reported in
|
|
# ST Application Note AN3321.
|
|
# - Modifications on the top layer:
|
|
# 1. remove R137 and C57, located near the SMII PHY U18;
|
|
# 2. remove R172 and C75, located near the SMII PHY U19;
|
|
# 3. remove R207 and C90, located near the SMII PHY U20;
|
|
# 4. remove C236, located near the SMII PHY U21;
|
|
# 5. remove U12, located near the JTAG connector;
|
|
# 6. solder together pins 7, 8 and 9 of U12;
|
|
# 7. solder together pins 11, 12, 13, 14, 15, 16, 17 and 18 of U12.
|
|
# - Modifications on the bottom layer:
|
|
# 8. replace reset chip U11 with a STM6315SDW13F;
|
|
# 9. add 0 ohm resistor R329. It is located close to JTAG connector.
|
|
#
|
|
# Date: 2009-10-31
|
|
# Author: Antonio Borneo <borneo.antonio@gmail.com>
|
|
|
|
|
|
# Modified boards has SRST on JTAG connector
|
|
set BOARD_HAS_SRST 1
|
|
source [find board/spear310evb20.cfg]
|