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2 Commits
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Author SHA1 Message Date
imi415 2239e5e6dc
Added eLCDIF drivers, modified liner scripts.
continuous-integration/drone/push Build is passing Details
2021-02-08 23:09:12 +08:00
imi415 0482ec6dd2
Added SEMC drivers, refined scripts. 2021-02-08 22:37:11 +08:00
35 changed files with 5071 additions and 133 deletions
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4
CMakeLists.txt
View File

@ -79,6 +79,10 @@ include(component_lists_MIMXRT1052)
include(component_serial_manager_uart_MIMXRT1052)
include(driver_semc_MIMXRT1052)
include(driver_elcdif_MIMXRT1052)
include(driver_lpuart_MIMXRT1052)
include(device_MIMXRT1052_startup_MIMXRT1052)

4
MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
View File

@ -41,6 +41,8 @@ MEMORY
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01800000
m_sdram_ncache (RW) : ORIGIN = 0x81800000, LENGTH = 0x00800000
}
/* Define output sections */
@ -207,7 +209,7 @@ SECTIONS
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_sdram_ncache
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);

6
MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld
View File

@ -38,6 +38,8 @@ MEMORY
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01800000
m_sdram_ncache (RW) : ORIGIN = 0x81800000, LENGTH = 0x00800000
}
/* Define output sections */
@ -174,7 +176,7 @@ SECTIONS
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_sdram_ncache
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
@ -194,7 +196,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
} > m_data2
.heap :
{

6
MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld
View File

@ -30,7 +30,7 @@ ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81E00000 - HEAP_SIZE;
NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81800000 - HEAP_SIZE;
NCACHE_HEAP_SIZE = DEFINED(__heap_noncacheable__) ? HEAP_SIZE : 0x0000;
/* Specify the memory areas */
@ -38,8 +38,8 @@ MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01E00000 : 0x01E00000 - HEAP_SIZE
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00200000 - HEAP_SIZE : 0x00200000
m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01800000 : 0x01800000 - HEAP_SIZE
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00800000 - HEAP_SIZE : 0x00800000
m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_heap (RW) : ORIGIN = NCACHE_HEAP_START, LENGTH = HEAP_SIZE

2
board/board.h
View File

@ -30,7 +30,7 @@
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
#ifndef BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
#define BOARD_DEBUG_UART_BAUDRATE (921600)
#endif /* BOARD_DEBUG_UART_BAUDRATE */
/*! @brief The USER_LED used for board */

6
board/clock_config.c
View File

@ -84,7 +84,7 @@ outputs:
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 150 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
@ -97,7 +97,7 @@ settings:
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.SEMC_PODF.scale, value: '4', locked: true}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
@ -231,7 +231,7 @@ void BOARD_BootClockRUN(void)
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
CLOCK_SetDiv(kCLOCK_SemcDiv, 3);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */

10
board/clock_config.c.bak
View File

@ -1,9 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
@ -25,7 +19,7 @@ product: Clocks v7.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 0.7.9
processor_version: 9.0.0
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@ -252,7 +246,7 @@ void BOARD_BootClockRUN(void)
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);

2
board/clock_config.h
View File

@ -72,7 +72,7 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL

6
board/clock_config.h.bak
View File

@ -1,9 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_

206
board/peripherals.c
View File

@ -55,7 +55,7 @@ instance:
- lpuartConfig:
- clockSource: 'LpuartClock'
- lpuartSrcClkFreq: 'BOARD_BootClockRUN'
- baudRate_Bps: '115200'
- baudRate_Bps: '921600'
- parityMode: 'kLPUART_ParityDisabled'
- dataBitsCount: 'kLPUART_EightDataBits'
- isMsb: 'false'
@ -70,11 +70,10 @@ instance:
- rxIdleConfig: 'kLPUART_IdleCharacter1'
- enableTx: 'true'
- enableRx: 'true'
- quick_selection: 'QuickSelection1'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
const lpuart_config_t LPUART1_config = {
.baudRate_Bps = 115200UL,
.baudRate_Bps = 921600UL,
.parityMode = kLPUART_ParityDisabled,
.dataBitsCount = kLPUART_EightDataBits,
.isMsb = false,
@ -95,6 +94,205 @@ static void LPUART1_init(void) {
LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE);
}
/***********************************************************************************************************************
* SEMC initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'SEMC'
- type: 'semc'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'semc_84a769c198c91c527e11dcec2f5b4b81'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'SEMC'
- config_sets:
- fsl_semc:
- enableDCD: 'false'
- clockConfig:
- clockSource: 'kSEMC_ClkSrcPeri'
- clockSourceFreq: 'BOARD_BootClockRUN'
- semc_config_t:
- dqsMode: 'kSEMC_Loopbackdqspad'
- cmdTimeoutCycles: '0'
- busTimeoutCycles: '0'
- queueWeight:
- queueaEnable: 'false'
- queueaWeight:
- structORvalue: 'structure'
- queueaConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- slaveHitNoswitch: '0'
- queuebEnable: 'false'
- queuebWeight:
- structORvalue: 'structure'
- queuebConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- weightPagehit: '0'
- bankRotation: '0'
- semc_sdram_config_t:
- csxPinMux: 'kSEMC_MUXCSX0'
- semcSdramCs: 'kSEMC_SDRAM_CS0'
- address: '0x80000000'
- memsize_input: '32MB'
- portSize: 'kSEMC_PortSize16Bit'
- burstLen: 'kSEMC_Sdram_BurstLen1'
- columnAddrBitNum: 'kSEMC_SdramColunm_9bit'
- casLatency: 'kSEMC_LatencyThree'
- tPrecharge2Act_Ns: '18'
- tAct2ReadWrite_Ns: '18'
- tRefreshRecovery_Ns: '127'
- tWriteRecovery_Ns: '12'
- tCkeOff_Ns: '42'
- tAct2Prechage_Ns: '42'
- tSelfRefRecovery_Ns: '67'
- tRefresh2Refresh_Ns: '60'
- tAct2Act_Ns: '60'
- tPrescalePeriod_Ns: '160'
- tIdleTimeout_Ns: '0'
- refreshPeriod_nsPerRow: '64'
- refreshUrgThreshold: '64'
- refreshBurstLen: '1'
- sdramArray: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
semc_config_t SEMC_config = {
.dqsMode = kSEMC_Loopbackdqspad,
.cmdTimeoutCycles = 0U,
.busTimeoutCycles = 0U,
.queueWeight = {
.queueaEnable = false,
.queueaWeight = {
.queueaConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.slaveHitNoswitch = 0UL
},
},
.queuebEnable = false,
.queuebWeight = {
.queuebConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.weightPagehit = 0UL,
.bankRotation = 0UL
},
}
}
};
semc_sdram_config_t SEMC_sdram_struct = {
.csxPinMux = kSEMC_MUXCSX0,
.address = 0x80000000UL,
.memsize_kbytes = 32768,
.portSize = kSEMC_PortSize16Bit,
.burstLen = kSEMC_Sdram_BurstLen1,
.columnAddrBitNum = kSEMC_SdramColunm_9bit,
.casLatency = kSEMC_LatencyThree,
.tPrecharge2Act_Ns = 18U,
.tAct2ReadWrite_Ns = 18U,
.tRefreshRecovery_Ns = 127U,
.tWriteRecovery_Ns = 12U,
.tCkeOff_Ns = 42U,
.tAct2Prechage_Ns = 42U,
.tSelfRefRecovery_Ns = 67U,
.tRefresh2Refresh_Ns = 60U,
.tAct2Act_Ns = 60U,
.tPrescalePeriod_Ns = 160UL,
.tIdleTimeout_Ns = 0UL,
.refreshPeriod_nsPerRow = 64UL,
.refreshUrgThreshold = 64UL,
.refreshBurstLen = 1U,
};
static void SEMC_init(void) {
/* Initialize SEMC peripheral. */
SEMC_Init(SEMC_PERIPHERAL, &SEMC_config);
/* Initialize SEMC SDRAM. */
SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000);
}
/***********************************************************************************************************************
* LCDIF initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'LCDIF'
- type: 'elcdif'
- mode: 'rgbMode'
- custom_name_enabled: 'false'
- type_id: 'elcdif_1c39bcb43ed1a24bc8980672c7378576'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'LCDIF'
- config_sets:
- fsl_elcdif:
- config:
- panelWidthInt: '800'
- panelHeightInt: '480'
- hsw: '1'
- hfp: '22'
- hbp: '46'
- vsw: '1'
- vfp: '22'
- vbp: '23'
- frameRate: '60 Hz'
- polarityFlags_st:
- vSyncActive: 'kELCDIF_VsyncActiveLow'
- hSyncActive: 'kELCDIF_HsyncActiveLow'
- dataEnableActive: 'kELCDIF_DataEnableActiveLow'
- driveDataClkEdge: 'kELCDIF_DriveDataOnFallingClkEdge'
- bufferName: 'defaultBuffer'
- bufferAlign: '64'
- pixelFormat: 'kELCDIF_PixelFormatXRGB8888'
- dataBus: 'kELCDIF_DataBus16Bit'
- enablePxpHandShake: 'false'
- start: 'false'
- isInterruptEnabled: 'true'
- elcdifInterruptSources: 'kELCDIF_CurFrameDoneInterruptEnable'
- interrupt:
- IRQn: 'LCDIF_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'true'
- priority: '5'
- enable_custom_name: 'false'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* RGB mode configuration */
const elcdif_rgb_mode_config_t LCDIF_rgbConfig = {
.panelWidth = LCDIF_PANEL_WIDTH,
.panelHeight = LCDIF_PANEL_HEIGHT,
.hsw = 1U,
.hfp = 22U,
.hbp = 46U,
.vsw = 1U,
.vfp = 22U,
.vbp = 23U,
.polarityFlags = (kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | kELCDIF_DriveDataOnFallingClkEdge),
.bufferAddr = (uint32_t) LCDIF_Buffer[0],
.pixelFormat = kELCDIF_PixelFormatXRGB8888,
.dataBus = kELCDIF_DataBus16Bit
};
/* RGB buffer */
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH], LCDIF_RGB_BUFFER_ALIGN);
static void LCDIF_init(void) {
/* RGB mode initialization */
ELCDIF_RgbModeInit(LCDIF_PERIPHERAL, &LCDIF_rgbConfig);
/* Enable interrupts */
ELCDIF_EnableInterrupts(LCDIF_PERIPHERAL, (kELCDIF_CurFrameDoneInterruptEnable));
/* Interrupt vector LCDIF_IRQn priority settings in the NVIC. */
NVIC_SetPriority(LCDIF_LCDIF_IRQN, LCDIF_LCDIF_IRQ_PRIORITY);
/* Enable interrupt LCDIF_IRQn request in the NVIC. */
EnableIRQ(LCDIF_LCDIF_IRQN);
}
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
@ -102,6 +300,8 @@ void BOARD_InitPeripherals(void)
{
/* Initialize components */
LPUART1_init();
SEMC_init();
LCDIF_init();
}
/***********************************************************************************************************************

187
board/peripherals.c.bak
View File

@ -34,11 +34,198 @@ component:
**********************************************************************************************************************/
#include "peripherals.h"
/***********************************************************************************************************************
* BOARD_InitPeripherals functional group
**********************************************************************************************************************/
/***********************************************************************************************************************
* LPUART1 initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'LPUART1'
- type: 'lpuart'
- mode: 'polling'
- custom_name_enabled: 'false'
- type_id: 'lpuart_54a65a580e3462acdbacefd5299e0cac'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'LPUART1'
- config_sets:
- lpuartConfig_t:
- lpuartConfig:
- clockSource: 'LpuartClock'
- lpuartSrcClkFreq: 'BOARD_BootClockRUN'
- baudRate_Bps: '921600'
- parityMode: 'kLPUART_ParityDisabled'
- dataBitsCount: 'kLPUART_EightDataBits'
- isMsb: 'false'
- stopBitCount: 'kLPUART_OneStopBit'
- txFifoWatermark: '0'
- rxFifoWatermark: '1'
- enableRxRTS: 'false'
- enableTxCTS: 'false'
- txCtsSource: 'kLPUART_CtsSourcePin'
- txCtsConfig: 'kLPUART_CtsSampleAtStart'
- rxIdleType: 'kLPUART_IdleTypeStartBit'
- rxIdleConfig: 'kLPUART_IdleCharacter1'
- enableTx: 'true'
- enableRx: 'true'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
const lpuart_config_t LPUART1_config = {
.baudRate_Bps = 921600UL,
.parityMode = kLPUART_ParityDisabled,
.dataBitsCount = kLPUART_EightDataBits,
.isMsb = false,
.stopBitCount = kLPUART_OneStopBit,
.txFifoWatermark = 0U,
.rxFifoWatermark = 1U,
.enableRxRTS = false,
.enableTxCTS = false,
.txCtsSource = kLPUART_CtsSourcePin,
.txCtsConfig = kLPUART_CtsSampleAtStart,
.rxIdleType = kLPUART_IdleTypeStartBit,
.rxIdleConfig = kLPUART_IdleCharacter1,
.enableTx = true,
.enableRx = true
};
static void LPUART1_init(void) {
LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE);
}
/***********************************************************************************************************************
* SEMC initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'SEMC'
- type: 'semc'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'semc_84a769c198c91c527e11dcec2f5b4b81'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'SEMC'
- config_sets:
- fsl_semc:
- enableDCD: 'false'
- clockConfig:
- clockSource: 'kSEMC_ClkSrcPeri'
- clockSourceFreq: 'BOARD_BootClockRUN'
- semc_config_t:
- dqsMode: 'kSEMC_Loopbackdqspad'
- cmdTimeoutCycles: '0'
- busTimeoutCycles: '0'
- queueWeight:
- queueaEnable: 'false'
- queueaWeight:
- structORvalue: 'structure'
- queueaConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- slaveHitNoswitch: '0'
- queuebEnable: 'false'
- queuebWeight:
- structORvalue: 'structure'
- queuebConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- weightPagehit: '0'
- bankRotation: '0'
- semc_sdram_config_t:
- csxPinMux: 'kSEMC_MUXCSX0'
- semcSdramCs: 'kSEMC_SDRAM_CS0'
- address: '0x80000000'
- memsize_input: '32MB'
- portSize: 'kSEMC_PortSize16Bit'
- burstLen: 'kSEMC_Sdram_BurstLen1'
- columnAddrBitNum: 'kSEMC_SdramColunm_9bit'
- casLatency: 'kSEMC_LatencyThree'
- tPrecharge2Act_Ns: '18'
- tAct2ReadWrite_Ns: '18'
- tRefreshRecovery_Ns: '127'
- tWriteRecovery_Ns: '12'
- tCkeOff_Ns: '42'
- tAct2Prechage_Ns: '42'
- tSelfRefRecovery_Ns: '67'
- tRefresh2Refresh_Ns: '60'
- tAct2Act_Ns: '60'
- tPrescalePeriod_Ns: '160'
- tIdleTimeout_Ns: '0'
- refreshPeriod_nsPerRow: '64'
- refreshUrgThreshold: '64'
- refreshBurstLen: '1'
- sdramArray: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
semc_config_t SEMC_config = {
.dqsMode = kSEMC_Loopbackdqspad,
.cmdTimeoutCycles = 0U,
.busTimeoutCycles = 0U,
.queueWeight = {
.queueaEnable = false,
.queueaWeight = {
.queueaConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.slaveHitNoswitch = 0UL
},
},
.queuebEnable = false,
.queuebWeight = {
.queuebConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.weightPagehit = 0UL,
.bankRotation = 0UL
},
}
}
};
semc_sdram_config_t SEMC_sdram_struct = {
.csxPinMux = kSEMC_MUXCSX0,
.address = 0x80000000UL,
.memsize_kbytes = 32768,
.portSize = kSEMC_PortSize16Bit,
.burstLen = kSEMC_Sdram_BurstLen1,
.columnAddrBitNum = kSEMC_SdramColunm_9bit,
.casLatency = kSEMC_LatencyThree,
.tPrecharge2Act_Ns = 18U,
.tAct2ReadWrite_Ns = 18U,
.tRefreshRecovery_Ns = 127U,
.tWriteRecovery_Ns = 12U,
.tCkeOff_Ns = 42U,
.tAct2Prechage_Ns = 42U,
.tSelfRefRecovery_Ns = 67U,
.tRefresh2Refresh_Ns = 60U,
.tAct2Act_Ns = 60U,
.tPrescalePeriod_Ns = 160UL,
.tIdleTimeout_Ns = 0UL,
.refreshPeriod_nsPerRow = 64UL,
.refreshUrgThreshold = 64UL,
.refreshBurstLen = 1U,
};
static void SEMC_init(void) {
/* Initialize SEMC peripheral. */
SEMC_Init(SEMC_PERIPHERAL, &SEMC_config);
/* Initialize SEMC SDRAM. */
SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000);
}
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void)
{
/* Initialize components */
LPUART1_init();
SEMC_init();
}
/***********************************************************************************************************************

27
board/peripherals.h
View File

@ -12,6 +12,8 @@
#include "fsl_common.h"
#include "fsl_lpuart.h"
#include "fsl_clock.h"
#include "fsl_semc.h"
#include "fsl_elcdif.h"
#if defined(__cplusplus)
extern "C" {
@ -25,11 +27,36 @@ extern "C" {
#define LPUART1_PERIPHERAL LPUART1
/* Definition of the clock source frequency */
#define LPUART1_CLOCK_SOURCE 80000000UL
/* BOARD_InitPeripherals defines for SEMC */
/* Definition of peripheral ID. */
#define SEMC_PERIPHERAL SEMC
/* Definition of peripheral ID */
#define LCDIF_PERIPHERAL LCDIF
/* Definition of the expected display clock frequency */
#define LCDIF_EXPECTED_DCLK_FREQ 27425640UL
/* Definition of the panel width */
#define LCDIF_PANEL_WIDTH 800
/* Definition of the panel height */
#define LCDIF_PANEL_HEIGHT 480
/* Definition of the RGB buffer alignment */
#define LCDIF_RGB_BUFFER_ALIGN 64
/* LCDIF interrupt vector ID (number). */
#define LCDIF_LCDIF_IRQN LCDIF_IRQn
/* LCDIF interrupt vector priority. */
#define LCDIF_LCDIF_IRQ_PRIORITY 5
/* LCDIF interrupt handler identifier. */
#define LCDIF_LCDIF_IRQHANDLER LCDIF_IRQHandler
/***********************************************************************************************************************
* Global variables
**********************************************************************************************************************/
extern const lpuart_config_t LPUART1_config;
extern semc_config_t SEMC_config;
extern semc_sdram_config_t SEMC_sdram_struct;
/* RGB mode configuration */
extern const elcdif_rgb_mode_config_t LCDIF_rgbConfig;
/* RGB buffer */
extern uint32_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH];
/***********************************************************************************************************************
* Initialization functions

27
board/peripherals.h.bak
View File

@ -6,10 +6,37 @@
#ifndef _PERIPHERALS_H_
#define _PERIPHERALS_H_
/***********************************************************************************************************************
* Included files
**********************************************************************************************************************/
#include "fsl_common.h"
#include "fsl_lpuart.h"
#include "fsl_clock.h"
#include "fsl_semc.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/* Definitions for BOARD_InitPeripherals functional group */
/* Definition of peripheral ID */
#define LPUART1_PERIPHERAL LPUART1
/* Definition of the clock source frequency */
#define LPUART1_CLOCK_SOURCE 80000000UL
/* BOARD_InitPeripherals defines for SEMC */
/* Definition of peripheral ID. */
#define SEMC_PERIPHERAL SEMC
/***********************************************************************************************************************
* Global variables
**********************************************************************************************************************/
extern const lpuart_config_t LPUART1_config;
extern semc_config_t SEMC_config;
extern semc_sdram_config_t SEMC_sdram_struct;
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/

122
board/pin_mux.c
View File

@ -38,6 +38,67 @@ BOARD_InitPins:
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
- {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
- {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
- {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00}
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04}
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05}
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06}
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07}
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08}
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09}
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10}
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11}
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12}
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13}
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14}
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15}
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00}
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01}
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02}
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03}
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03}
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02}
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@ -52,6 +113,67 @@ void BOARD_InitPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}

126
board/pin_mux.c.bak
View File

@ -1,10 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@ -13,11 +6,12 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v7.0
product: Pins v9.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 6.0.0
processor_version: 9.0.0
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@ -44,6 +38,47 @@ BOARD_InitPins:
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
- {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
- {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
- {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@ -54,34 +89,53 @@ BOARD_InitPins:
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}
/***********************************************************************************************************************

356
board/pin_mux.h
View File

@ -47,6 +47,362 @@ void BOARD_InitBootPins(void);
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_EMC_09 (coord C2), SEMC_A0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_10 (coord G1), SEMC_A1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_11 (coord G3), SEMC_A2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_12 (coord H1), SEMC_A3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_13 (coord A6), SEMC_A4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_14 (coord B6), SEMC_A5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_15 (coord B1), SEMC_A6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_16 (coord A5), SEMC_A7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_17 (coord A4), SEMC_A8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_18 (coord B2), SEMC_A9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_23 (coord G2), SEMC_A10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_19 (coord B4), SEMC_A11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_20 (coord A3), SEMC_A12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_24 (coord D3), SEMC_CAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_27 (coord A2), SEMC_CKE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_26 (coord B3), SEMC_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDIO_SIGNAL CSX /*!< Signal name */
#define BOARD_INITPINS_ENET_MDIO_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
#define BOARD_INITPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_00 (coord E3), SEMC_D0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_01 (coord F3), SEMC_D1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_02 (coord F4), SEMC_D2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_03 (coord G4), SEMC_D3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_04 (coord F2), SEMC_D4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_05 (coord G5), SEMC_D5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_06 (coord H5), SEMC_D6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_07 (coord H4), SEMC_D7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_30 (coord C6), SEMC_D8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_31 (coord C5), SEMC_D9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (coord D5), SEMC_D10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_33 (coord C4), SEMC_D11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_34 (coord D4), SEMC_D12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_35 (coord E5), SEMC_D13 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (coord C3), SEMC_D14 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (coord E4), SEMC_D15 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_25 (coord D2), SEMC_RAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_40 (coord A7), ENET_MDC */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDC_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDC_SIGNAL semc_rdy /*!< Signal name */
/* GPIO_EMC_28 (coord D1), SEMC_WE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/* GPIO_B0_00 (coord D7), LCDIF_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */
/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_B1_00 (coord A11), LCDIF_D12 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_B1_01 (coord B11), LCDIF_D13 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_B1_02 (coord C11), LCDIF_D14 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_B1_03 (coord D11), LCDIF_D15 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */
/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */
/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.

257
board/pin_mux.h.bak
View File

@ -1,10 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@ -44,6 +37,256 @@ extern "C" {
*/
void BOARD_InitBootPins(void);
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_EMC_09 (coord C2), SEMC_A0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_10 (coord G1), SEMC_A1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_11 (coord G3), SEMC_A2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_12 (coord H1), SEMC_A3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_13 (coord A6), SEMC_A4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_14 (coord B6), SEMC_A5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_15 (coord B1), SEMC_A6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_16 (coord A5), SEMC_A7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_17 (coord A4), SEMC_A8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_18 (coord B2), SEMC_A9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_23 (coord G2), SEMC_A10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_19 (coord B4), SEMC_A11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_20 (coord A3), SEMC_A12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_24 (coord D3), SEMC_CAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_27 (coord A2), SEMC_CKE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_26 (coord B3), SEMC_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDIO_SIGNAL CSX /*!< Signal name */
#define BOARD_INITPINS_ENET_MDIO_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
#define BOARD_INITPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_00 (coord E3), SEMC_D0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_01 (coord F3), SEMC_D1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_02 (coord F4), SEMC_D2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_03 (coord G4), SEMC_D3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_04 (coord F2), SEMC_D4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_05 (coord G5), SEMC_D5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_06 (coord H5), SEMC_D6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_07 (coord H4), SEMC_D7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_30 (coord C6), SEMC_D8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_31 (coord C5), SEMC_D9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (coord D5), SEMC_D10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_33 (coord C4), SEMC_D11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_34 (coord D4), SEMC_D12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_35 (coord E5), SEMC_D13 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (coord C3), SEMC_D14 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (coord E4), SEMC_D15 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_25 (coord D2), SEMC_RAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_40 (coord A7), ENET_MDC */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDC_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDC_SIGNAL semc_rdy /*!< Signal name */
/* GPIO_EMC_28 (coord D1), SEMC_WE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.

12
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@ -0,0 +1,12 @@
#!/bin/sh
if [[ -z "${ENV}" ]]; then
export ENV=debug
fi
rm build/${ENV} -rf && mkdir -p build/${ENV} && cd build/${ENV}
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" \
-G "Unix Makefiles" -DCMAKE_BUILD_TYPE=${ENV} \
../.. && make $@

19
build_all.sh
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@ -1,9 +1,5 @@
#!/bin/sh
if [ ! -d "build" ]; then mkdir build; fi
cd build
TARGETS=(
"debug"
"release"
@ -13,15 +9,12 @@ TARGETS=(
"flexspi_nor_release"
)
bash clean.sh
for TARGET in "${TARGETS[@]}" ; do
if [ -d "${TARGET}" ]; then rm -rf ${TARGET}; fi
mkdir ${TARGET} && cd ${TARGET}
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=${TARGET} ../.. && make -j1
ENV=${TARGET} bash build.sh $@
RET=$?
if [ ! 0 -eq ${RET} ]; then exit ${RET}; fi
cd ..
if [[ ! 0 -eq ${RET} ]]; then
exit ${RET}
fi
done

7
build_debug.sh
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@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
make -j 2>&1 | tee build_log.txt

7
build_flexspi_nor_debug.sh
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@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_debug .
make -j 2>&1 | tee build_log.txt

7
build_flexspi_nor_release.sh
View File

@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_release .
make -j 2>&1 | tee build_log.txt

7
build_release.sh
View File

@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
make -j 2>&1 | tee build_log.txt

7
build_sdram_debug.sh
View File

@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=sdram_debug .
make -j 2>&1 | tee build_log.txt

7
build_sdram_release.sh
View File

@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=sdram_release .
make -j 2>&1 | tee build_log.txt

4
clean.sh
View File

@ -1,3 +1,3 @@
#!/bin/sh
rm -rf debug release sdram_debug sdram_release flexspi_nor_debug flexspi_nor_release CMakeFiles
rm -rf Makefile cmake_install.cmake CMakeCache.txt
rm build -rf

17
drivers/driver_elcdif_MIMXRT1052.cmake Normal file
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@ -0,0 +1,17 @@
if(NOT DRIVER_ELCDIF_MIMXRT1052_INCLUDED)
set(DRIVER_ELCDIF_MIMXRT1052_INCLUDED true CACHE BOOL "driver_elcdif component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_elcdif.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/.
)
include(driver_common_MIMXRT1052)
endif()

17
drivers/driver_semc_MIMXRT1052.cmake Normal file
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@ -0,0 +1,17 @@
if(NOT DRIVER_SEMC_MIMXRT1052_INCLUDED)
set(DRIVER_SEMC_MIMXRT1052_INCLUDED true CACHE BOOL "driver_semc component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_semc.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/.
)
include(driver_common_MIMXRT1052)
endif()

386
drivers/fsl_elcdif.c Normal file
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@ -0,0 +1,386 @@
/*
* Copyright 2017-2019 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_elcdif.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.elcdif"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for ELCDIF module.
*
* @param base ELCDIF peripheral base address
*/
static uint32_t ELCDIF_GetInstance(LCDIF_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to ELCDIF bases for each instance. */
static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to eLCDIF apb_clk for each instance. */
static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS;
#if defined(LCDIF_PERIPH_CLOCKS)
/*! @brief Pointers to eLCDIF pix_clk for each instance. */
static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS;
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief The control register value to select different pixel format. */
static const elcdif_pixel_format_reg_t s_pixelFormatReg[] = {
/* kELCDIF_PixelFormatRAW8 */
{/* Register CTRL. */
LCDIF_CTRL_WORD_LENGTH(1U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
/* kELCDIF_PixelFormatRGB565 */
{/* Register CTRL. */
LCDIF_CTRL_WORD_LENGTH(0U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
/* kELCDIF_PixelFormatRGB666 */
{/* Register CTRL. */
LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
/* kELCDIF_PixelFormatXRGB8888 */
{/* Register CTRL. 24-bit. */
LCDIF_CTRL_WORD_LENGTH(3U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
/* kELCDIF_PixelFormatRGB888 */
{/* Register CTRL. 24-bit. */
LCDIF_CTRL_WORD_LENGTH(3U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
};
/*******************************************************************************
* Codes
******************************************************************************/
static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++)
{
if (s_elcdifBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_elcdifBases));
return instance;
}
/*!
* brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
*
* This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
* to the configuration structure.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
{
assert(NULL != config);
assert((uint32_t)config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = ELCDIF_GetInstance(base);
/* Enable the clock. */
CLOCK_EnableClock(s_elcdifApbClocks[instance]);
#if defined(LCDIF_PERIPH_CLOCKS)
CLOCK_EnableClock(s_elcdifPixClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset. */
ELCDIF_Reset(base);
base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) |
LCDIF_CTRL_DOTCLK_MODE_MASK | /* RGB mode. */
LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */
LCDIF_CTRL_MASTER_MASK;
base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1;
base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) |
((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT);
base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | /* Data enable signal. */
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | /* VSYNC period in the unit of display clock. */
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */
(uint32_t)config->polarityFlags | (uint32_t)config->vsw;
base->VDCTRL1 =
(uint32_t)config->vsw + (uint32_t)config->panelHeight + (uint32_t)config->vfp + (uint32_t)config->vbp;
base->VDCTRL2 =
((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) |
(((uint32_t)config->hfp + (uint32_t)config->hbp + (uint32_t)config->panelWidth + (uint32_t)config->hsw))
<< LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT;
base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) |
(((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT);
base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK |
((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT);
base->CUR_BUF = config->bufferAddr;
base->NEXT_BUF = config->bufferAddr;
}
/*!
* brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
*
* This function sets the configuration structure to default values.
* The default configuration is set to the following values.
* code
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow |
kELCDIF_HsyncActiveLow |
kELCDIF_DataEnableActiveLow |
kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
code
*
* param config Pointer to the eLCDIF configuration structure.
*/
void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = (uint32_t)kELCDIF_VsyncActiveLow | (uint32_t)kELCDIF_HsyncActiveLow |
(uint32_t)kELCDIF_DataEnableActiveLow | (uint32_t)kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
}
/*!
* brief Set the pixel format in RGB (DOTCLK) mode.
*
* param base eLCDIF peripheral base address.
* param pixelFormat The pixel format.
*/
void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat)
{
assert((uint32_t)pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
base->CTRL = (base->CTRL & ~(LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK |
LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK | LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)) |
s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl;
base->CTRL1 = s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl1;
}
/*!
* brief Deinitializes the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Deinit(LCDIF_Type *base)
{
ELCDIF_Reset(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = ELCDIF_GetInstance(base);
/* Disable the clock. */
#if defined(LCDIF_PERIPH_CLOCKS)
CLOCK_DisableClock(s_elcdifPixClocks[instance]);
#endif
CLOCK_DisableClock(s_elcdifApbClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Stop display in RGB (DOTCLK) mode and wait until finished.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_RgbModeStop(LCDIF_Type *base)
{
base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
/* Wait for data transfer finished. */
while (0U != (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK))
{
}
}
/*!
* brief Reset the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Reset(LCDIF_Type *base)
{
/*
* ELCDIF reset workflow:
*
* 1. Ungate clock.
* 2. Trigger the software reset.
* 3. The software reset finished when clk_gate bit is set.
* 4. Ungate the clock.
* 5. Release the reset.
*/
/* Ungate clock. */
base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
/*
* If already in reset state, release the reset.
* If not, trigger reset.
*/
if (0U == (base->CTRL & LCDIF_CTRL_SFTRST_MASK))
{
/* Trigger reset. */
base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK;
/* Reset is not finished until CLK_GATE is set. */
while (0U == (base->CTRL & LCDIF_CTRL_CLKGATE_MASK))
{
}
/* Ungate the clock. */
base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
}
/* Release the reset. */
base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK;
}
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
/*!
* brief Set the configuration for alpha surface buffer.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
{
assert(NULL != config);
base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
base->AS_BUF = config->bufferAddr;
base->AS_NEXT_BUF = config->bufferAddr;
}
/*!
* brief Set the alpha surface blending configuration.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
{
assert(NULL != config);
uint32_t reg;
reg = base->AS_CTRL;
reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK |
LCDIF_AS_CTRL_ALPHA_CTRL_MASK);
reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) |
LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode));
if (config->invertAlpha)
{
reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK;
}
base->AS_CTRL = reg;
}
#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
/*!
* brief Load the LUT value.
*
* This function loads the LUT value to the specific LUT memory, user can
* specify the start entry index.
*
* param base eLCDIF peripheral base address.
* param lut Which LUT to load.
* param startIndex The start index of the LUT entry to update.
* param lutData The LUT data to load.
* param count Count of p lutData.
* retval kStatus_Success Initialization success.
* retval kStatus_InvalidArgument Wrong argument.
*/
status_t ELCDIF_UpdateLut(
LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
{
volatile uint32_t *regLutAddr;
volatile uint32_t *regLutData;
uint32_t i;
status_t status;
/* Only has 256 entries. */
if (startIndex + count > ELCDIF_LUT_ENTRY_NUM)
{
status = kStatus_InvalidArgument;
}
else
{
if (kELCDIF_Lut0 == lut)
{
regLutAddr = &(base->LUT0_ADDR);
regLutData = &(base->LUT0_DATA);
}
else
{
regLutAddr = &(base->LUT1_ADDR);
regLutData = &(base->LUT1_DATA);
}
*regLutAddr = startIndex;
for (i = 0; i < count; i++)
{
*regLutData = lutData[i];
}
status = kStatus_Success;
}
return status;
}
#endif /* FSL_FEATURE_LCDIF_HAS_LUT */

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/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ELCDIF_H_
#define _FSL_ELCDIF_H_
#include "fsl_common.h"
/*!
* @addtogroup elcdif
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief eLCDIF driver version */
#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/* All IRQ flags in CTRL1 register. */
#define ELCDIF_CTRL1_IRQ_MASK \
(LCDIF_CTRL1_BM_ERROR_IRQ_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK | \
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
/* All IRQ enable control bits in CTRL1 register. */
#define ELCDIF_CTRL1_IRQ_EN_MASK \
(LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK | \
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
/* All IRQ flags in AS_CTRL register. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
#define ELCDIF_AS_CTRL_IRQ_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
#else
#define ELCDIF_AS_CTRL_IRQ_MASK 0U
#endif
/* All IRQ enable control bits in AS_CTRL register. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
#define ELCDIF_AS_CTRL_IRQ_EN_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
#else
#define ELCDIF_AS_CTRL_IRQ_EN_MASK 0U
#endif
#if ((ELCDIF_CTRL1_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_MASK) || (ELCDIF_AS_CTRL_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_EN_MASK))
#error Interrupt bits overlap, need to update the interrupt functions.
#endif
/* LUT memory entery number. */
#define ELCDIF_LUT_ENTRY_NUM 256U
/*!
* @brief eLCDIF signal polarity flags
*/
enum _elcdif_polarity_flags
{
kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */
kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */
kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */
kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */
kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */
kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */
kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data
on rising clock edge. */
kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling
clock edge, capture data
on rising clock edge. */
};
/*!
* @brief The eLCDIF interrupts to enable.
*/
enum _elcdif_interrupt_enable
{
kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */
kELCDIF_CurFrameDoneInterruptEnable =
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
kELCDIF_VsyncEdgeInterruptEnable =
LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
kELCDIF_SciSyncOnInterruptEnable =
LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */
#endif
};
/*!
* @brief The eLCDIF interrupt status flags.
*/
enum _elcdif_interrupt_flags
{
kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */
kELCDIF_CurFrameDone =
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
kELCDIF_VsyncEdge = LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
kELCDIF_SciSyncOn = LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */
#endif
};
/*!
* @brief eLCDIF status flags
*/
enum _elcdif_status_flags
{
kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */
kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */
kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */
kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */
#if defined(LCDIF_STAT_BUSY_MASK)
kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */
#endif
#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
kELCDIF_CurDviField2 = LCDIF_STAT_DVI_CURRENT_FIELD_MASK, /*!< Current DVI filed, if set, then current filed is 2,
otherwise current filed is 1. */
#endif
};
/*!
* @brief The pixel format.
*
* This enumerator should be defined together with the array s_pixelFormatReg.
* To support new pixel format, enhance this enumerator and s_pixelFormatReg.
*/
typedef enum _elcdif_pixel_format
{
kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */
kELCDIF_PixelFormatRGB565 = 1, /*!< RGB565, two pixel use 32 bits. */
kELCDIF_PixelFormatRGB666 = 2, /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused,
upper 2 bits of other bytes unused. */
kELCDIF_PixelFormatXRGB8888 = 3, /*!< XRGB8888 unpacked, one pixel uses 32 bits, high byte unused. */
kELCDIF_PixelFormatRGB888 = 4, /*!< RGB888 packed, one pixel uses 24 bits. */
} elcdif_pixel_format_t;
/*! @brief The LCD data bus type. */
typedef enum _elcdif_lcd_data_bus
{
kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */
kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */
kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */
kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */
} elcdif_lcd_data_bus_t;
/*!
* @brief The register value when using different pixel format.
*
* These register bits control the pixel format:
* - CTRL[DATA_FORMAT_24_BIT]
* - CTRL[DATA_FORMAT_18_BIT]
* - CTRL[DATA_FORMAT_16_BIT]
* - CTRL[WORD_LENGTH]
* - CTRL1[BYTE_PACKING_FORMAT]
*/
typedef struct _elcdif_pixel_format_reg
{
uint32_t regCtrl; /*!< Value of register CTRL. */
uint32_t regCtrl1; /*!< Value of register CTRL1. */
} elcdif_pixel_format_reg_t;
/*!
* @brief eLCDIF configure structure for RGB mode (DOTCLK mode).
*/
typedef struct _elcdif_rgb_mode_config
{
uint16_t panelWidth; /*!< Display panel width, pixels per line. */
uint16_t panelHeight; /*!< Display panel height, how many lines per panel. */
uint8_t hsw; /*!< HSYNC pulse width. */
uint8_t hfp; /*!< Horizontal front porch. */
uint8_t hbp; /*!< Horizontal back porch. */
uint8_t vsw; /*!< VSYNC pulse width. */
uint8_t vfp; /*!< Vrtical front porch. */
uint8_t vbp; /*!< Vertical back porch. */
uint32_t polarityFlags; /*!< OR'ed value of @ref _elcdif_polarity_flags, used to contol the signal polarity. */
uint32_t bufferAddr; /*!< Frame buffer address. */
elcdif_pixel_format_t pixelFormat; /*!< Pixel format. */
elcdif_lcd_data_bus_t dataBus; /*!< LCD data bus. */
} elcdif_rgb_mode_config_t;
/*!
* @brief eLCDIF alpha surface pixel format.
*/
typedef enum _elcdif_as_pixel_format
{
kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
} elcdif_as_pixel_format_t;
/*!
* @brief eLCDIF alpha surface buffer configuration.
*/
typedef struct _elcdif_as_buffer_config
{
uint32_t bufferAddr; /*!< Buffer address. */
elcdif_as_pixel_format_t pixelFormat; /*!< Pixel format. */
} elcdif_as_buffer_config_t;
/*!
* @brief eLCDIF alpha mode during blending.
*/
typedef enum _elcdif_alpha_mode
{
kELCDIF_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */
kELCDIF_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */
kELCDIF_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined
alpha value will be used for blend, for example, pixel alpha set
set to 200, user defined alpha set to 100, then the reault alpha
is 200 * 100 / 255. */
kELCDIF_AlphaRop /*!< Raster operation. */
} elcdif_alpha_mode_t;
/*!
* @brief eLCDIF ROP mode during blending.
*
* Explanation:
* - AS: Alpha surface
* - PS: Process surface
* - nAS: Alpha surface NOT value
* - nPS: Process surface NOT value
*/
typedef enum _elcdif_rop_mode
{
kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */
kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */
kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */
kELCDIF_RopNot = 0x7, /*!< nPS. */
kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */
kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */
} elcdif_rop_mode_t;
/*!
* @brief eLCDIF alpha surface blending configuration.
*/
typedef struct _elcdif_as_blend_config
{
uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kELCDIF_AlphaOverride or @ref
kELCDIF_AlphaRop. */
bool invertAlpha; /*!< Set true to invert the alpha. */
elcdif_alpha_mode_t alphaMode; /*!< Alpha mode. */
elcdif_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kELCDIF_AlphaRop. */
} elcdif_as_blend_config_t;
/*!
* @brief eLCDIF LUT
*
* The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel
* before output to external displayer.
*
* There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address
* determins which memory to use.
*/
typedef enum _elcdif_lut
{
kELCDIF_Lut0 = 0, /*!< LUT 0. */
kELCDIF_Lut1, /*!< LUT 1. */
} elcdif_lut_t;
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @name eLCDIF initialization and de-initialization
* @{
*/
/*!
* @brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
*
* This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
* to the configuration structure.
*
* @param base eLCDIF peripheral base address.
* @param config Pointer to the configuration structure.
*/
void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config);
/*!
* @brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
*
* This function sets the configuration structure to default values.
* The default configuration is set to the following values.
* @code
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow |
kELCDIF_HsyncActiveLow |
kELCDIF_DataEnableActiveLow |
kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
@endcode
*
* @param config Pointer to the eLCDIF configuration structure.
*/
void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config);
/*!
* @brief Deinitializes the eLCDIF peripheral.
*
* @param base eLCDIF peripheral base address.
*/
void ELCDIF_Deinit(LCDIF_Type *base);
/* @} */
/*!
* @name Module operation
* @{
*/
/*!
* @brief Set the pixel format in RGB (DOTCLK) mode.
*
* @param base eLCDIF peripheral base address.
* @param pixelFormat The pixel format.
*/
void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat);
/*!
* @brief Start to display in RGB (DOTCLK) mode.
*
* @param base eLCDIF peripheral base address.
*/
static inline void ELCDIF_RgbModeStart(LCDIF_Type *base)
{
base->CTRL_SET = LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK;
}
/*!
* @brief Stop display in RGB (DOTCLK) mode and wait until finished.
*
* @param base eLCDIF peripheral base address.
*/
void ELCDIF_RgbModeStop(LCDIF_Type *base);
/*!
* @brief Set the next frame buffer address to display.
*
* @param base eLCDIF peripheral base address.
* @param bufferAddr The frame buffer address to set.
*/
static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr)
{
base->NEXT_BUF = bufferAddr;
}
/*!
* @brief Reset the eLCDIF peripheral.
*
* @param base eLCDIF peripheral base address.
*/
void ELCDIF_Reset(LCDIF_Type *base);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN) && FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN)
/*!
* @brief Pull up or down the reset pin for the externel LCD controller.
*
* @param base eLCDIF peripheral base address.
* @param pullUp True to pull up reset pin, false to pull down.
*/
static inline void ELCDIF_PullUpResetPin(LCDIF_Type *base, bool pullUp)
{
if (pullUp)
{
base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK;
}
else
{
base->CTRL1_CLR = LCDIF_CTRL1_RESET_MASK;
}
}
#endif
/*!
* @brief Enable or disable the hand shake with PXP.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnablePxpHandShake(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->CTRL_SET = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK;
}
else
{
base->CTRL_CLR = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK;
}
}
/* @} */
/*!
* @name Status
* @{
*/
/*!
* @brief Get the CRC value of the frame sent out.
*
* When a frame is sent complete (the interrupt @ref kELCDIF_CurFrameDone assert), this function
* can be used to get the CRC value of the frame sent.
*
* @param base eLCDIF peripheral base address.
* @return The CRC value.
*
* @note The CRC value is dependent on the LCD_DATABUS_WIDTH.
*/
static inline uint32_t ELCDIF_GetCrcValue(LCDIF_Type *base)
{
return base->CRC_STAT;
}
/*!
* @brief Get the bus master error virtual address.
*
* When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function
* can get the virtual address at which the AXI master received an error
* response from the slave.
*
* @param base eLCDIF peripheral base address.
* @return The error virtual address.
*/
static inline uint32_t ELCDIF_GetBusMasterErrorAddr(LCDIF_Type *base)
{
return base->BM_ERROR_STAT;
}
/*!
* @brief Get the eLCDIF status.
*
* The status flags are returned as a mask value, application could check the
* corresponding bit. Example:
*
* @code
uint32_t statusFlags;
statusFlags = ELCDIF_GetStatus(LCDIF);
if (kELCDIF_LFifoFull & statusFlags)
{
}
if (kELCDIF_TxFifoEmpty & statusFlags)
{
}
@endcode
*
* @param base eLCDIF peripheral base address.
* @return The mask value of status flags, it is OR'ed value of @ref _elcdif_status_flags.
*/
static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base)
{
return base->STAT & (LCDIF_STAT_LFIFO_FULL_MASK | LCDIF_STAT_LFIFO_EMPTY_MASK | LCDIF_STAT_TXFIFO_FULL_MASK |
LCDIF_STAT_TXFIFO_EMPTY_MASK
#if defined(LCDIF_STAT_BUSY_MASK)
| LCDIF_STAT_BUSY_MASK
#endif
#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
| LCDIF_STAT_DVI_CURRENT_FIELD_MASK
#endif
);
}
/*!
* @brief Get current count in Latency buffer (LFIFO).
*
* @param base eLCDIF peripheral base address.
* @return The LFIFO current count
*/
static inline uint32_t ELCDIF_GetLFifoCount(LCDIF_Type *base)
{
return (base->STAT & LCDIF_STAT_LFIFO_COUNT_MASK) >> LCDIF_STAT_LFIFO_COUNT_SHIFT;
}
/* @} */
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enables eLCDIF interrupt requests.
*
* @param base eLCDIF peripheral base address.
* @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable.
*/
static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask)
{
base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
base->AS_CTRL |= (mask & ELCDIF_AS_CTRL_IRQ_EN_MASK);
#endif
}
/*!
* @brief Disables eLCDIF interrupt requests.
*
* @param base eLCDIF peripheral base address.
* @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable.
*/
static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask)
{
base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_EN_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_EN_MASK);
#endif
}
/*!
* @brief Get eLCDIF interrupt peding status.
*
* @param base eLCDIF peripheral base address.
* @return Interrupt pending status, OR'ed value of _elcdif_interrupt_flags.
*/
static inline uint32_t ELCDIF_GetInterruptStatus(LCDIF_Type *base)
{
uint32_t flags;
flags = (base->CTRL1 & ELCDIF_CTRL1_IRQ_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
flags |= (base->AS_CTRL & ELCDIF_AS_CTRL_IRQ_MASK);
#endif
return flags;
}
/*!
* @brief Clear eLCDIF interrupt peding status.
*
* @param base eLCDIF peripheral base address.
* @param mask of the flags to clear, OR'ed value of _elcdif_interrupt_flags.
*/
static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask)
{
base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_MASK);
#endif
}
/* @} */
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
/*!
* @name Alpha surface
* @{
*/
/*!
* @brief Set the configuration for alpha surface buffer.
*
* @param base eLCDIF peripheral base address.
* @param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config);
/*!
* @brief Set the alpha surface blending configuration.
*
* @param base eLCDIF peripheral base address.
* @param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config);
/*!
* @brief Set the next alpha surface buffer address.
*
* @param base eLCDIF peripheral base address.
* @param bufferAddr Alpha surface buffer address.
*/
static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32_t bufferAddr)
{
base->AS_NEXT_BUF = bufferAddr;
}
/*!
* @brief Set the overlay color key.
*
* If a pixel in the current overlay image with a color that falls in the range
* from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface
* pixel value for that location.
*
* @param base eLCDIF peripheral base address.
* @param colorKeyLow Color key low range.
* @param colorKeyHigh Color key high range.
*
* @note Colorkey operations are higher priority than alpha or ROP operations
*/
static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
{
base->AS_CLRKEYLOW = colorKeyLow;
base->AS_CLRKEYHIGH = colorKeyHigh;
}
/*!
* @brief Enable or disable the color key.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableOverlayColorKey(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->AS_CTRL |= LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK;
}
else
{
base->AS_CTRL &= ~LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK;
}
}
/*!
* @brief Enable or disable the alpha surface.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableAlphaSurface(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->AS_CTRL |= LCDIF_AS_CTRL_AS_ENABLE_MASK;
}
else
{
base->AS_CTRL &= ~LCDIF_AS_CTRL_AS_ENABLE_MASK;
}
}
/*!
* @brief Enable or disable the process surface.
*
* Process surface is the normal frame buffer. The process surface content
* is controlled by ::ELCDIF_SetNextBufferAddr.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableProcessSurface(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->AS_CTRL &= ~LCDIF_AS_CTRL_PS_DISABLE_MASK;
}
else
{
base->AS_CTRL |= LCDIF_AS_CTRL_PS_DISABLE_MASK;
}
}
/* @} */
#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
/*!
* @name LUT
*
* The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel
* before output to external displayer.
*
* There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address
* determins which memory to use.
*
* @{
*/
/*!
* @brief Enable or disable the LUT.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableLut(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->LUT_CTRL &= ~LCDIF_LUT_CTRL_LUT_BYPASS_MASK;
}
else
{
base->LUT_CTRL |= LCDIF_LUT_CTRL_LUT_BYPASS_MASK;
}
}
/*!
* @brief Load the LUT value.
*
* This function loads the LUT value to the specific LUT memory, user can
* specify the start entry index.
*
* @param base eLCDIF peripheral base address.
* @param lut Which LUT to load.
* @param startIndex The start index of the LUT entry to update.
* @param lutData The LUT data to load.
* @param count Count of @p lutData.
* @retval kStatus_Success Initialization success.
* @retval kStatus_InvalidArgument Wrong argument.
*/
status_t ELCDIF_UpdateLut(
LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count);
/* @} */
#endif /* FSL_FEATURE_LCDIF_HAS_LUT */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/* @} */
#endif /*_FSL_ELCDIF_H_*/

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/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_SEMC_H_
#define _FSL_SEMC_H_
#include "fsl_common.h"
/*!
* @addtogroup semc
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief SEMC driver version 2.3.1. */
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
/*@}*/
/*! @brief SEMC status, _semc_status. */
enum
{
kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), /*!< Invalid device type. */
kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), /*!< IP command execution error. */
kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), /*!< AXI command execution error. */
kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), /*!< Invalid memory sie. */
kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), /*!< Invalid IP command data size. */
kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), /*!< Invalid address port width. */
kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), /*!< Invalid data port width. */
kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), /*!< Invalid SW pinmux selection. */
kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), /*!< Invalid burst length */
/*! Invalid column address bit width. */
kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), /*!< Invalid base address. */
kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), /*!< Invalid timer setting. */
};
/*! @brief SEMC memory device type. */
typedef enum _semc_mem_type
{
kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
kSEMC_MemType_SRAM, /*!< SRAM */
kSEMC_MemType_NOR, /*!< NOR */
kSEMC_MemType_NAND, /*!< NAND */
kSEMC_MemType_8080 /*!< 8080. */
} semc_mem_type_t;
/*! @brief SEMC WAIT/RDY polarity. */
typedef enum _semc_waitready_polarity
{
kSEMC_LowActive = 0, /*!< Low active. */
kSEMC_HighActive, /*!< High active. */
} semc_waitready_polarity_t;
/*! @brief SEMC SDRAM Chip selection . */
typedef enum _semc_sdram_cs
{
kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
} semc_sdram_cs_t;
/*! @brief SEMC SRAM Chip selection . */
typedef enum _semc_sram_cs
{
#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U)
kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
kSEMC_SRAM_CS1, /*!< SEMC SRAM CS1. */
kSEMC_SRAM_CS2, /*!< SEMC SRAM CS2. */
kSEMC_SRAM_CS3 /*!< SEMC SRAM CS3. */
#else
kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
} semc_sram_cs_t;
/*! @brief SEMC NAND device type. */
typedef enum _semc_nand_access_type
{
kSEMC_NAND_ACCESS_BY_AXI = 0, /*!< Access to NAND flash by AXI bus. */
kSEMC_NAND_ACCESS_BY_IPCMD, /*!< Access to NAND flash by IP bus. */
} semc_nand_access_type_t;
/*! @brief SEMC interrupts . */
typedef enum _semc_interrupt_enable
{
kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
} semc_interrupt_enable_t;
/*! @brief SEMC IP command data size in bytes. */
typedef enum _semc_ipcmd_datasize
{
kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
} semc_ipcmd_datasize_t;
/*! @brief SEMC auto-refresh timing. */
typedef enum _semc_refresh_time
{
kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
} semc_refresh_time_t;
/*! @brief CAS latency */
typedef enum _semc_caslatency
{
kSEMC_LatencyOne = 1, /*!< Latency 1. */
kSEMC_LatencyTwo, /*!< Latency 2. */
kSEMC_LatencyThree, /*!< Latency 3. */
} semc_caslatency_t;
/*! @brief SEMC sdram column address bit number. */
typedef enum _semc_sdram_column_bit_num
{
kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
kSEMC_SdramColunm_11bit, /*!< 11 bit. */
kSEMC_SdramColunm_10bit, /*!< 10 bit. */
kSEMC_SdramColunm_9bit, /*!< 9 bit. */
#if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT)
kSEMC_SdramColunm_8bit, /*!< 8 bit. */
#endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */
} semc_sdram_column_bit_num_t;
/*! @brief SEMC sdram burst length. */
typedef enum _semc_sdram_burst_len
{
/*! According to ERR050577, Auto-refresh command may possibly fail to be triggered during
long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. */
#if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U)
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
#else
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
#endif /* FSL_FEATURE_SEMC_ERRATA_050577 */
} sem_sdram_burst_len_t;
/*! @brief SEMC nand column address bit number. */
typedef enum _semc_nand_column_bit_num
{
kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
kSEMC_NandColum_15bit, /*!< 15 bit. */
kSEMC_NandColum_14bit, /*!< 14 bit. */
kSEMC_NandColum_13bit, /*!< 13 bit. */
kSEMC_NandColum_12bit, /*!< 12 bit. */
kSEMC_NandColum_11bit, /*!< 11 bit. */
kSEMC_NandColum_10bit, /*!< 10 bit. */
kSEMC_NandColum_9bit, /*!< 9 bit. */
} semc_nand_column_bit_num_t;
/*! @brief SEMC nand burst length. */
typedef enum _semc_nand_burst_len
{
kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
} sem_nand_burst_len_t;
/*! @brief SEMC nor/sram column address bit number. */
typedef enum _semc_norsram_column_bit_num
{
kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
kSEMC_NorColum_11bit, /*!< 11 bit. */
kSEMC_NorColum_10bit, /*!< 10 bit. */
kSEMC_NorColum_9bit, /*!< 9 bit. */
kSEMC_NorColum_8bit, /*!< 8 bit. */
kSEMC_NorColum_7bit, /*!< 7 bit. */
kSEMC_NorColum_6bit, /*!< 6 bit. */
kSEMC_NorColum_5bit, /*!< 5 bit. */
kSEMC_NorColum_4bit, /*!< 4 bit. */
kSEMC_NorColum_3bit, /*!< 3 bit. */
kSEMC_NorColum_2bit /*!< 2 bit. */
} semc_norsram_column_bit_num_t;
/*! @brief SEMC nor/sram burst length. */
typedef enum _semc_norsram_burst_len
{
kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
} sem_norsram_burst_len_t;
/*! @brief SEMC dbi column address bit number. */
typedef enum _semc_dbi_column_bit_num
{
kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
} semc_dbi_column_bit_num_t;
/*! @brief SEMC dbi burst length. */
typedef enum _semc_dbi_burst_len
{
kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
} sem_dbi_burst_len_t;
/*! @brief SEMC IOMUXC. */
typedef enum _semc_iomux_pin
{
kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
} semc_iomux_pin;
/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
typedef enum _semc_iomux_nora27_pin
{
kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
} semc_iomux_nora27_pin;
/*! @brief SEMC port size. */
typedef enum _semc_port_size
{
kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
kSEMC_PortSize16Bit, /*!< 16-Bit port size. */
#if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U)
kSEMC_PortSize32Bit /*!< 32-Bit port size. */
#endif /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */
} smec_port_size_t;
/*! @brief SEMC address mode. */
typedef enum _semc_addr_mode
{
kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
} semc_addr_mode_t;
/*! @brief SEMC DQS read strobe mode. */
typedef enum _semc_dqs_mode
{
kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
} semc_dqs_mode_t;
/*! @brief SEMC ADV signal active polarity. */
typedef enum _semc_adv_polarity
{
kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
kSEMC_AdvActiveHigh, /*!< Adv active high. */
} semc_adv_polarity_t;
/*! @brief SEMC sync mode. */
typedef enum _semc_sync_mode
{
kSEMC_AsyncMode = 0, /*!< Async mode. */
kSEMC_SyncMode, /*!< Sync mode. */
} semc_sync_mode_t;
/*! @brief SEMC ADV signal level control. */
typedef enum _semc_adv_level_control
{
kSEMC_AdvHigh = 0, /*!< Adv is high during address hold state. */
kSEMC_AdvLow, /*!< Adv is low during address hold state. */
} semc_adv_level_control_t;
/*! @brief SEMC RDY signal active polarity. */
typedef enum _semc_rdy_polarity
{
kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
kSEMC_RdyActivehigh, /*!< Adv active low. */
} semc_rdy_polarity_t;
/*! @brief SEMC IP command for NAND: address mode. */
typedef enum _semc_ipcmd_nand_addrmode
{
kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
} semc_ipcmd_nand_addrmode_t;
/*! @brief SEMC IP command for NAND： command mode. */
typedef enum _semc_ipcmd_nand_cmdmode
{
kSEMC_NANDCM_Command = 0x2U, /*!< command. */
kSEMC_NANDCM_CommandHold, /*!< Command hold. */
kSEMC_NANDCM_CommandAddress, /*!< Command address. */
kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
kSEMC_NANDCM_CommandRead, /*!< Command read. */
kSEMC_NANDCM_CommandWrite, /*!< Command write. */
kSEMC_NANDCM_Read, /*!< Read. */
kSEMC_NANDCM_Write /*!< Write. */
} semc_ipcmd_nand_cmdmode_t;
/*! @brief SEMC NAND address option. */
typedef enum _semc_nand_address_option
{
kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
} semc_nand_address_option_t;
/*! @brief SEMC IP command for NOR. */
typedef enum _semc_ipcmd_nor_dbi
{
kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
kSEMC_NORDBICM_Write /*!< NOR write. */
} semc_ipcmd_nor_dbi_t;
/*! @brief SEMC IP command for SRAM. */
typedef enum _semc_ipcmd_sram
{
kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
} semc_ipcmd_sram_t;
/*! @brief SEMC IP command for SDARM. */
typedef enum _semc_ipcmd_sdram
{
kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
} semc_ipcmd_sdram_t;
/*! @brief SEMC SDRAM configuration structure.
*
* 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
* should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
* Take refer to BR0~BR3 register in RM for details.
* 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
* it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
* The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
* idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
* similar to prescalePeriod_N16Cycle.
*
*/
typedef struct _semc_sdram_config
{
semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
smec_port_size_t portSize; /*!< Port size. */
sem_sdram_burst_len_t burstLen; /*!< Burst length. */
semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_caslatency_t casLatency; /*!< CAS latency. */
uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
uint8_t refreshBurstLen; /*!< Refresh burst length. */
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
read data. */
#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_sdram_config_t;
/*! @brief SEMC NAND device timing configuration structure. */
typedef struct _semc_nand_timing_config
{
uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
uint8_t tReLow_Ns; /*!< RE low time: tRP. */
uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
} semc_nand_timing_config_t;
/*! @brief SEMC NAND configuration structure. */
typedef struct _semc_nand_config
{
semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
uint32_t axiAddress; /*!< The base address for AXI nand. */
uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
uint32_t ipgAddress; /*!< The base address for IPG nand . */
uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
bool edoModeEnabled; /*!< EDO mode enabled. */
semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
sem_nand_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
} semc_nand_config_t;
/*! @brief SEMC NOR configuration structure. */
typedef struct _semc_nor_config
{
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
uint8_t addrPortWidth; /*!< The address port width. */
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_addr_mode_t addrMode; /*!< Address mode. */
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
uint8_t tCeHold_Ns; /*!< The CE hold time. */
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
uint8_t tAddrHold_Ns; /*!< The address hold time. */
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
#endif
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
#endif
uint8_t latencyCount; /*!< Latency count for sync mode. */
uint8_t readCycle; /*!< Read cycle time for sync mode. */
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
read data. */
#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_nor_config_t;
/*! @brief SEMC SRAM configuration structure. */
typedef struct _semc_sram_config
{
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
uint8_t addrPortWidth; /*!< The address port width. */
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
semc_addr_mode_t addrMode; /*!< Address mode. */
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
semc_sync_mode_t syncMode; /*!< Sync mode. */
#endif /* SEMC_SRAMCR4_SYNCEN_MASK */
#if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK)
bool waitEnable; /*!< Wait enable. */
#endif /* SEMC_SRAMCR0_WAITEN_MASK */
#if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK)
uint8_t waitSample; /*!< Wait sample. */
#endif /* SEMC_SRAMCR0_WAITSP_MASK */
#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
semc_adv_level_control_t advLevelCtrl; /*!< ADV# level control during address hold state, 1: low, 0: high. */
#endif /* SEMC_SRAMCR4_ADVH_MASK */
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
uint8_t tCeHold_Ns; /*!< The CE hold time. */
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME)
uint8_t readHoldTime_Ns; /*!< read hold time. */
#endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
uint8_t tAddrHold_Ns; /*!< The address hold time. */
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
uint8_t latencyCount; /*!< Latency count for sync mode. */
uint8_t readCycle; /*!< Read cycle time for sync mode. */
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
read data. */
#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_sram_config_t;
/*! @brief SEMC DBI configuration structure. */
typedef struct _semc_dbi_config
{
semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
sem_dbi_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
uint8_t tWexLow_Ns; /*!< WEX low time. */
uint8_t tWexHigh_Ns; /*!< WEX high time. */
uint8_t tRdxLow_Ns; /*!< RDX low time. */
uint8_t tRdxHigh_Ns; /*!< RDX high time. */
uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
} semc_dbi_config_t;
/*! @brief SEMC AXI queue a weight setting structure. */
typedef struct _semc_queuea_weight_struct
{
uint32_t qos : 4; /*!< weight of qos for queue 0 . */
uint32_t aging : 4; /*!< weight of aging for queue 0.*/
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
} semc_queuea_weight_struct_t;
/*! @brief SEMC AXI queue a weight setting union. */
typedef union _semc_queuea_weight
{
semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
} semc_queuea_weight_t;
/*! @brief SEMC AXI queue b weight setting structure. */
typedef struct _semc_queueb_weight_struct
{
uint32_t qos : 4; /*!< weight of qos for queue 1. */
uint32_t aging : 4; /*!< weight of aging for queue 1.*/
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
} semc_queueb_weight_struct_t;
/*! @brief SEMC AXI queue b weight setting union. */
typedef union _semc_queueb_weight
{
semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
} semc_queueb_weight_t;
/*! @brief SEMC AXI queue weight setting. */
typedef struct _semc_axi_queueweight
{
bool queueaEnable; /*!< Enable queue a. */
semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
bool queuebEnable; /*!< Enable queue b. */
semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
} semc_axi_queueweight_t;
/*!
* @brief SEMC configuration structure.
*
* busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
* 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
* cmdTimeoutCycles: is used for command execution timeout cycles. it's
* similar to the busTimeoutCycles.
*/
typedef struct _semc_config_t
{
semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
} semc_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name SEMC Initialization and De-initialization
* @{
*/
/*!
* @brief Gets the SEMC default basic configuration structure.
*
* The purpose of this API is to get the default SEMC
* configure structure for SEMC_Init(). User may use the initialized
* structure unchanged in SEMC_Init(), or modify some fields of the
* structure before calling SEMC_Init().
* Example:
@code
semc_config_t config;
SEMC_GetDefaultConfig(&config);
@endcode
* @param config The SEMC configuration structure pointer.
*/
void SEMC_GetDefaultConfig(semc_config_t *config);
/*!
* @brief Initializes SEMC.
* This function ungates the SEMC clock and initializes SEMC.
* This function must be called before calling any other SEMC driver functions.
*
* @param base SEMC peripheral base address.
* @param configure The SEMC configuration structure pointer.
*/
void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
/*!
* @brief Deinitializes the SEMC module and gates the clock.
*
* This function gates the SEMC clock. As a result, the SEMC module doesn't work after
* calling this function, for some IDE, calling this API may cause the next downloading
* operation failed. so, please call this API cautiously. Additional, users can
* using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
* operation in drivers.
*
* @param base SEMC peripheral base address.
*/
void SEMC_Deinit(SEMC_Type *base);
/* @} */
/*!
* @name SEMC Configuration Operation For Each Memory Type
* @{
*/
/*!
* @brief Configures SDRAM controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param cs The chip selection.
* @param config The sdram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures NAND controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The nand configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures NOR controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The nor configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures SRAM controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param cs The chip selection.
* @param config The sram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
semc_sram_cs_t cs,
semc_sram_config_t *config,
uint32_t clkSrc_Hz);
/*!
* @brief Configures SRAM controller in SEMC.
* @deprecated Do not use this function. It has been superceded by @ref SEMC_ConfigureSRAMWithChipSelection.
* @param base SEMC peripheral base address.
* @param config The sram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures DBI controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The dbi configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
/* @} */
/*!
* @name SEMC Interrupt Operation
* @{
*/
/*!
* @brief Enables the SEMC interrupt.
*
* This function enables the SEMC interrupts according to the provided mask. The mask
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
* For example, to enable the IP command done and error interrupt, do the following.
* @code
* SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
* @endcode
*
* @param base SEMC peripheral base address.
* @param mask SEMC interrupts to enable. This is a logical OR of the
* enumeration :: semc_interrupt_enable_t.
*/
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
{
base->INTEN |= mask;
}
/*!
* @brief Disables the SEMC interrupt.
*
* This function disables the SEMC interrupts according to the provided mask. The mask
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
* For example, to disable the IP command done and error interrupt, do the following.
* @code
* SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
* @endcode
*
* @param base SEMC peripheral base address.
* @param mask SEMC interrupts to disable. This is a logical OR of the
* enumeration :: semc_interrupt_enable_t.
*/
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
{
base->INTEN &= ~mask;
}
/*!
* @brief Gets the SEMC status.
*
* This function gets the SEMC interrupts event status.
* User can use the a logical OR of enumeration member as a mask.
* See @ref semc_interrupt_enable_t.
*
* @param base SEMC peripheral base address.
* @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
*/
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
{
return (base->INTR != 0x00U) ? true : false;
}
/*!
* @brief Clears the SEMC status flag state.
*
* The following status register flags can be cleared SEMC interrupt status.
*
* @param base SEMC base pointer
* @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
*/
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
{
base->INTR |= mask;
}
/* @} */
/*!
* @name SEMC Memory Access Operation
* @{
*/
/*!
* @brief Check if SEMC is in idle.
*
* @param base SEMC peripheral base address.
* @return True SEMC is in idle, false is not in idle.
*/
static inline bool SEMC_IsInIdle(SEMC_Type *base)
{
return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false;
}
/*!
* @brief SEMC IP command access.
*
* @param base SEMC peripheral base address.
* @param type SEMC memory type. refer to "semc_mem_type_t"
* @param address SEMC device address.
* @param command SEMC IP command.
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
* For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
* For SRAM device, take refer to "semc_ipcmd_sram_t".
* For SDRAM device, take refer to "semc_ipcmd_sdram_t".
* @param write Data for write access.
* @param read Data pointer for read data out.
*/
status_t SEMC_SendIPCommand(
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
/*!
* @brief Build SEMC IP command for NAND.
*
* This function build SEMC NAND IP command. The command is build of user command code,
* SEMC address mode and SEMC command mode.
*
* @param userCommand NAND device normal command.
* @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
* @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
*/
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
semc_ipcmd_nand_addrmode_t addrMode,
semc_ipcmd_nand_cmdmode_t cmdMode)
{
return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU);
}
/*!
* @brief Check if the NAND device is ready.
*
* @param base SEMC peripheral base address.
* @return True NAND is ready, false NAND is not ready.
*/
static inline bool SEMC_IsNandReady(SEMC_Type *base)
{
return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false;
}
/*!
* @brief SEMC NAND device memory write through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NAND device address.
* @param data Data for write access.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NAND device memory read through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NAND device address.
* @param data Data pointer for data read out.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NOR device memory write through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NOR device address.
* @param data Data for write access.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NOR device memory read through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NOR device address.
* @param data Data pointer for data read out.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_SEMC_H_*/

36
imxrt1050.cfg Normal file
View File

@ -0,0 +1,36 @@
# NXP i.MX RT1050 family (Arm Cortex-M7 @ 600 MHz)
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imxrt1050
}
source [find target/swj-dp.tcl]
if { [info exists CPU_SWD_TAPID] } {
set _CPU_SWD_TAPID $CPU_SWD_TAPID
} else {
set _CPU_SWD_TAPID 0x0bd11477
}
if { [using_jtag] } {
set _CPU_TAPID 0
} else {
set _CPU_TAPID $_CPU_SWD_TAPID
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
set _TARGETNAME $_CHIPNAME
dap create $_TARGETNAME.dap -chain-position $_TARGETNAME.cpu
target create $_TARGETNAME cortex_m -dap $_TARGETNAME.dap
if { ![using_hla] } {
cortex_m reset_config sysresetreq
}
gdb_breakpoint_override hard
adapter speed 8000

306
rt1050_freertos_hello.mex
View File

@ -39,6 +39,16 @@
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
@ -77,6 +87,67 @@
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
<pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
<pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
<pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
<pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
<pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
<pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
<pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
<pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
<pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
<pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
<pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
<pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
<pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
<pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
<pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
<pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
<pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
<pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
<pin peripheral="SEMC" signal="CSX, 0" pin_num="C7" pin_signal="GPIO_EMC_41"/>
<pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/>
<pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
<pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
<pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
<pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
<pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
<pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
<pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
<pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
<pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
<pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
<pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
<pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
<pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
<pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
<pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
<pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
<pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
<pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
<pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
<pin peripheral="SEMC" signal="semc_rdy" pin_num="A7" pin_signal="GPIO_EMC_40"/>
<pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
<pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00"/>
<pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04"/>
<pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05"/>
<pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06"/>
<pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07"/>
<pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08"/>
<pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09"/>
<pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10"/>
<pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11"/>
<pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12"/>
<pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13"/>
<pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14"/>
<pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15"/>
<pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00"/>
<pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01"/>
<pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02"/>
<pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03"/>
<pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03"/>
<pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02"/>
<pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01"/>
</pins>
</function>
</functions_list>
@ -181,7 +252,7 @@
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
@ -195,7 +266,7 @@
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM.PLL3_SW_CLK_SEL" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="4" locked="true"/>
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
<setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
<setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
@ -390,6 +461,26 @@
<data type="Version">2.2.8</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.semc" description="SEMC Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.semc" description="Unsupported version of the SEMC Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">2.3.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.elcdif" description="elcdif not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.elcdif" description="Unsupported version of the elcdif in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">2.0.0</data>
</feature>
</dependency>
</dependencies>
<generated_project_files>
<file path="board/peripherals.c" update_enabled="true"/>
@ -418,14 +509,119 @@
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_clk" description="Signal CLK of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_enable" description="Signal ENABLE of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_hsync" description="Signal HSYNC of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_vsync" description="Signal VSYNC of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.00" description="Signal DATA of the channel 00 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.01" description="Signal DATA of the channel 01 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.02" description="Signal DATA of the channel 02 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.03" description="Signal DATA of the channel 03 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.04" description="Signal DATA of the channel 04 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.05" description="Signal DATA of the channel 05 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.06" description="Signal DATA of the channel 06 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.07" description="Signal DATA of the channel 07 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.08" description="Signal DATA of the channel 08 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.09" description="Signal DATA of the channel 09 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.10" description="Signal DATA of the channel 10 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.11" description="Signal DATA of the channel 11 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.12" description="Signal DATA of the channel 12 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.13" description="Signal DATA of the channel 13 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.14" description="Signal DATA of the channel 14 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.15" description="Signal DATA of the channel 15 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="routed" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="ClockOutput" resourceId="LCDIF_CLK_ROOT" description="LCDIF_CLK_ROOT is inactive." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
<feature name="frequency" evaluation="greaterThan">
<data type="Frequency" unit="Hz">0</data>
</feature>
</dependency>
</dependencies>
<instances>
<instance name="LPUART1" uuid="c4097945-c1a4-4198-901a-11b1297f9b3d" type="lpuart" type_id="lpuart_54a65a580e3462acdbacefd5299e0cac" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
<config_set name="lpuartConfig_t">
<struct name="lpuartConfig">
<setting name="clockSource" value="LpuartClock"/>
<setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
<setting name="baudRate_Bps" value="115200"/>
<setting name="baudRate_Bps" value="921600"/>
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
<setting name="isMsb" value="false"/>
@ -443,6 +639,108 @@
</struct>
</config_set>
</instance>
<instance name="SEMC" uuid="b2d43365-247f-4857-87c6-cf56b5ddcae5" type="semc" type_id="semc_84a769c198c91c527e11dcec2f5b4b81" mode="general" peripheral="SEMC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="fsl_semc">
<setting name="enableDCD" value="false"/>
<struct name="clockConfig">
<setting name="clockSource" value="kSEMC_ClkSrcPeri"/>
<setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
</struct>
<struct name="semc_config_t">
<setting name="dqsMode" value="kSEMC_Loopbackdqspad"/>
<setting name="cmdTimeoutCycles" value="0"/>
<setting name="busTimeoutCycles" value="0"/>
<struct name="queueWeight">
<setting name="queueaEnable" value="false"/>
<struct name="queueaWeight">
<setting name="structORvalue" value="structure"/>
<struct name="queueaConfig">
<setting name="qos" value="0"/>
<setting name="aging" value="0"/>
<setting name="slaveHitSwith" value="0"/>
<setting name="slaveHitNoswitch" value="0"/>
</struct>
</struct>
<setting name="queuebEnable" value="false"/>
<struct name="queuebWeight">
<setting name="structORvalue" value="structure"/>
<struct name="queuebConfig">
<setting name="qos" value="0"/>
<setting name="aging" value="0"/>
<setting name="slaveHitSwith" value="0"/>
<setting name="weightPagehit" value="0"/>
<setting name="bankRotation" value="0"/>
</struct>
</struct>
</struct>
</struct>
<struct name="semc_sdram_config_t">
<setting name="csxPinMux" value="kSEMC_MUXCSX0"/>
<setting name="semcSdramCs" value="kSEMC_SDRAM_CS0"/>
<setting name="address" value="0x80000000"/>
<setting name="memsize_input" value="32MB"/>
<setting name="portSize" value="kSEMC_PortSize16Bit"/>
<setting name="burstLen" value="kSEMC_Sdram_BurstLen1"/>
<setting name="columnAddrBitNum" value="kSEMC_SdramColunm_9bit"/>
<setting name="casLatency" value="kSEMC_LatencyThree"/>
<setting name="tPrecharge2Act_Ns" value="18"/>
<setting name="tAct2ReadWrite_Ns" value="18"/>
<setting name="tRefreshRecovery_Ns" value="127"/>
<setting name="tWriteRecovery_Ns" value="12"/>
<setting name="tCkeOff_Ns" value="42"/>
<setting name="tAct2Prechage_Ns" value="42"/>
<setting name="tSelfRefRecovery_Ns" value="67"/>
<setting name="tRefresh2Refresh_Ns" value="60"/>
<setting name="tAct2Act_Ns" value="60"/>
<setting name="tPrescalePeriod_Ns" value="160"/>
<setting name="tIdleTimeout_Ns" value="0"/>
<setting name="refreshPeriod_nsPerRow" value="64"/>
<setting name="refreshUrgThreshold" value="64"/>
<setting name="refreshBurstLen" value="1"/>
</struct>
<array name="sdramArray"/>
</config_set>
</instance>
<instance name="LCDIF" uuid="045e7c7e-f29e-4ee1-8f04-e6a3e59eebc4" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="fsl_elcdif">
<struct name="config">
<setting name="panelWidthInt" value="800"/>
<setting name="panelHeightInt" value="480"/>
<setting name="hsw" value="1"/>
<setting name="hfp" value="22"/>
<setting name="hbp" value="46"/>
<setting name="vsw" value="1"/>
<setting name="vfp" value="22"/>
<setting name="vbp" value="23"/>
<setting name="frameRate" value="60 Hz"/>
<struct name="polarityFlags_st">
<setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
<setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
<setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
<setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
</struct>
<setting name="bufferName" value="defaultBuffer"/>
<setting name="bufferAlign" value="64"/>
<setting name="pixelFormat" value="kELCDIF_PixelFormatXRGB8888"/>
<setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
<setting name="enablePxpHandShake" value="false"/>
<setting name="start" value="false"/>
</struct>
<setting name="isInterruptEnabled" value="true"/>
<set name="elcdifInterruptSources">
<selected>
<id>kELCDIF_CurFrameDoneInterruptEnable</id>
</selected>
</set>
<struct name="interrupt">
<setting name="IRQn" value="LCDIF_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="true"/>
<setting name="priority" value="5"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>

5
source/freertos_hello.c
View File

@ -17,6 +17,7 @@
#include "fsl_debug_console.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "peripherals.h"
#include "board.h"
/*******************************************************************************
@ -42,7 +43,9 @@ int main(void)
BOARD_ConfigMPU();
BOARD_InitBootPins();
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();
BOARD_InitDebugConsole();
if (xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) !=
pdPASS)
{
@ -63,6 +66,6 @@ static void hello_task(void *pvParameters)
for (;;)
{
PRINTF("Hello world.\r\n");
vTaskSuspend(NULL);
vTaskDelay(pdMS_TO_TICKS(400));
}
}