Added reset function.
continuous-integration/drone/push Build is passing Details

Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun 2023-05-30 00:13:49 +08:00
parent 26a7a36a69
commit 58b7d03a6a
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
6 changed files with 43 additions and 6 deletions

View File

@ -6,5 +6,6 @@
void ate_impl_i2c_init(void);
ate_ret_t ate_impl_i2c_read(void *handle, uint8_t *data, uint8_t len);
ate_ret_t ate_impl_i2c_write(void *handle, uint8_t *data, uint8_t len);
ate_ret_t ate_impl_delay(void *handle, uint32_t msec);
#endif // APP_ATE_IMPL_H

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@ -18,10 +18,12 @@ typedef enum {
typedef ate_ret_t (*ate_i2c_read_t)(void *handle, uint8_t *data, uint8_t len);
typedef ate_ret_t (*ate_i2c_write_t)(void *handle, uint8_t *data, uint8_t len);
typedef ate_ret_t (*ate_delay_t)(void *handle, uint32_t msec);
typedef struct {
ate_i2c_read_t read;
ate_i2c_write_t write;
ate_delay_t delay;
} ate_ops_t;
typedef struct {

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@ -11,7 +11,7 @@
#define ATE_REG_ID 0xFFU
#define ATE_REG_CFG_RST_Pos 15
#define ATe_REG_CFG_RST_Msk (1U << ATE_REG_CFG_RST_Pos)
#define ATE_REG_CFG_RST_Msk (1U << ATE_REG_CFG_RST_Pos)
#define ATE_REG_GPIO_CFG_MODE_Pos 0
#define ATE_REG_GPIO_CFG_MODE_Msk (3U << ATE_REG_GPIO_CFG_MODE_Pos)

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@ -4,6 +4,7 @@
#define ATE_COMPONENT_ID 0xEACE
static ate_ret_t ate_reset(ate_t *ate);
static ate_ret_t ate_read_id(ate_t *ate, uint16_t *id);
static ate_ret_t ate_read_register(ate_t *ate, uint8_t reg, uint16_t *data);
@ -12,6 +13,11 @@ static ate_ret_t ate_write_register(ate_t *ate, uint8_t reg, uint16_t data);
ate_ret_t ate_init(ate_t *ate) {
ate_ret_t ret = ATE_RET_SUCCESS;
ret = ate_reset(ate);
if (ret != ATE_RET_SUCCESS) {
return ret;
}
uint16_t id;
ret = ate_read_id(ate, &id);
@ -64,7 +70,7 @@ ate_ret_t ate_gpio_write(ate_t *ate, uint8_t pin, bool value) {
ate_ret_t ret = ATE_RET_SUCCESS;
uint16_t pin_data;
ret = ate_read_register(ate, ATE_REG_GPIO_DATA_IN, &pin_data);
ret = ate_read_register(ate, ATE_REG_GPIO_DATA_OUT, &pin_data);
if (ret != ATE_RET_SUCCESS) {
return ret;
}
@ -79,6 +85,27 @@ ate_ret_t ate_gpio_write(ate_t *ate, uint8_t pin, bool value) {
return ret;
}
static ate_ret_t ate_reset(ate_t *ate) {
ate_ret_t ret = ATE_RET_SUCCESS;
uint16_t cfg;
ret = ate_read_register(ate, ATE_REG_CFG, &cfg);
if (ret != ATE_RET_SUCCESS) {
return ret;
}
cfg |= ATE_REG_CFG_RST_Msk;
ret = ate_write_register(ate, ATE_REG_CFG, cfg);
if (ret != ATE_RET_SUCCESS) {
return ret;
}
ret = ate->ops.delay(ate, 120);
return ret;
}
static ate_ret_t ate_read_id(ate_t *ate, uint16_t *id) {
return ate_read_register(ate, ATE_REG_ID, id);
}

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@ -35,6 +35,12 @@ ate_ret_t ate_impl_i2c_write(void *handle, uint8_t *data, uint8_t len) {
return ATE_RET_SUCCESS;
}
ate_ret_t ate_impl_delay(void *handle, uint32_t msec) {
delay_ms(msec);
return ATE_RET_SUCCESS;
}
void i2c_lowlevel_init(i2c_handle_type *handle) {
if (handle->i2cx == I2C1) {
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);

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@ -13,6 +13,7 @@ static ate_t s_ate = {
{
.read = ate_impl_i2c_read,
.write = ate_impl_i2c_write,
.delay = ate_impl_delay,
},
};
@ -33,25 +34,25 @@ int main(void) {
bool pin_value = false;
if(ate_gpio_read(&s_ate, 0, &pin_value) != ATE_RET_SUCCESS) {
if (ate_gpio_read(&s_ate, 0, &pin_value) != ATE_RET_SUCCESS) {
printf("Failed to read GPIO value\r\n");
goto dead_loop;
}
if(ate_gpio_write(&s_ate, 0, 1) != ATE_RET_SUCCESS) {
if (ate_gpio_write(&s_ate, 0, 1) != ATE_RET_SUCCESS) {
printf("Failed to write pin.\r\n");
goto dead_loop;
}
if(ate_gpio_init(&s_ate, 0, ATE_GPIO_MODE_OUTPUT_PP) != ATE_RET_SUCCESS) {
if (ate_gpio_init(&s_ate, 0, ATE_GPIO_MODE_OUTPUT_PP) != ATE_RET_SUCCESS) {
printf("Failed to config pin.");
goto dead_loop;
}
if(ate_gpio_read(&s_ate, 0, &pin_value) != ATE_RET_SUCCESS) {
if (ate_gpio_read(&s_ate, 0, &pin_value) != ATE_RET_SUCCESS) {
printf("Failed to read GPIO value\r\n");
goto dead_loop;