generated from Embedded_Projects/CH32V307_Template
203 lines
9.7 KiB
ArmAsm
203 lines
9.7 KiB
ArmAsm
/********************************** (C) COPYRIGHT *******************************
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* File Name : startup_ch32v30x_D8C.s
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : CH32V307-CH32V305 vector table for eclipse toolchain.
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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.section .vectors,"ax",@progbits
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.global _start
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.align 4
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.option push
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.option norvc
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_start:
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j Reset_Handler /* Go! */
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/**
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* The only mode WCH didn't break is MODE 0, non-vectored exception.
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* We place the jump table here, but processed by software.
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*
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*/
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_vectors:
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j Exception_Handler /* 0: Exception */
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j Default_Handler /* 1: Reserved */
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j NMI_Handler /* 2: NMI */
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j Default_Handler /* 3: Reserved */
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j Default_Handler /* 4: Reserved */
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j Default_Handler /* 5: Reserved */
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j Default_Handler /* 6: Reserved */
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j Default_Handler /* 7: Reserved */
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j Default_Handler /* 8: Reserved */
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j Default_Handler /* 9: Reserved */
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j Default_Handler /* 10: Reserved */
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j Default_Handler /* 11: Reserved */
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j SysTick_Handler /* 12: SysTick */
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j Default_Handler /* 13: Reserved */
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j SW_Handler /* 14: Software */
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j Default_Handler /* 15: Reserved */
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j WWDG_IRQHandler /* 16: Window Watchdog */
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j PVD_IRQHandler /* 17: PVD through EXTI Line detect */
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j TAMPER_IRQHandler /* 18: TAMPER */
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j RTC_IRQHandler /* 19: RTC */
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j FLASH_IRQHandler /* 20: Flash */
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j RCC_IRQHandler /* 21: RCC */
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j EXTI0_IRQHandler /* 22: EXTI Line 0 */
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j EXTI1_IRQHandler /* 23: EXTI Line 1 */
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j EXTI2_IRQHandler /* 24: EXTI Line 2 */
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j EXTI3_IRQHandler /* 25: EXTI Line 3 */
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j EXTI4_IRQHandler /* 26: EXTI Line 4 */
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j DMA1_Channel1_IRQHandler /* 27: DMA1 Channel 1 */
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j DMA1_Channel2_IRQHandler /* 28: DMA1 Channel 2 */
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j DMA1_Channel3_IRQHandler /* 29: DMA1 Channel 3 */
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j DMA1_Channel4_IRQHandler /* 30: DMA1 Channel 4 */
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j DMA1_Channel5_IRQHandler /* 31: DMA1 Channel 5 */
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j DMA1_Channel6_IRQHandler /* 32: DMA1 Channel 6 */
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j DMA1_Channel7_IRQHandler /* 33: DMA1 Channel 7 */
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j ADC1_2_IRQHandler /* 34: ADC1_2 */
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j USB_HP_CAN1_TX_IRQHandler /* 35: USB HP and CAN1 TX */
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j USB_LP_CAN1_RX0_IRQHandler /* 36: USB LP and CAN1RX0 */
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j CAN1_RX1_IRQHandler /* 37: CAN1 RX1 */
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j CAN1_SCE_IRQHandler /* 38: CAN1 SCE */
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j EXTI9_5_IRQHandler /* 39: EXTI Line 9..5 */
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j TIM1_BRK_IRQHandler /* 40: TIM1 Break */
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j TIM1_UP_IRQHandler /* 41: TIM1 Update */
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j TIM1_TRG_COM_IRQHandler /* 42: TIM1 Trigger and Commutation */
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j TIM1_CC_IRQHandler /* 43: TIM1 Capture Compare */
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j TIM2_IRQHandler /* 44: TIM2 */
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j TIM3_IRQHandler /* 45: TIM3 */
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j TIM4_IRQHandler /* 46: TIM4 */
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j I2C1_EV_IRQHandler /* 47: I2C1 Event */
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j I2C1_ER_IRQHandler /* 48: I2C1 Error */
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j I2C2_EV_IRQHandler /* 49: I2C2 Event */
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j I2C2_ER_IRQHandler /* 50: I2C2 Error */
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j SPI1_IRQHandler /* 51: SPI1 */
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j SPI2_IRQHandler /* 52: SPI2 */
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j USART1_IRQHandler /* 53: USART1 */
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j USART2_IRQHandler /* 54: USART2 */
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j USART3_IRQHandler /* 55: USART3 */
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j EXTI15_10_IRQHandler /* 56: EXTI Line 15..10 */
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j RTCAlarm_IRQHandler /* 57: RTC Alarm through EXTI Line */
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j USBWakeUp_IRQHandler /* 58: USB Wakeup from suspend */
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j TIM8_BRK_IRQHandler /* 59: TIM8 Break */
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j TIM8_UP_IRQHandler /* 60: TIM8 Update */
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j TIM8_TRG_COM_IRQHandler /* 61: TIM8 Trigger and Commutation */
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j TIM8_CC_IRQHandler /* 62: TIM8 Capture Compare */
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j RNG_IRQHandler /* 63: RNG */
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j FSMC_IRQHandler /* 64: FSMC */
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j SDIO_IRQHandler /* 65: SDIO */
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j TIM5_IRQHandler /* 66: TIM5 */
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j SPI3_IRQHandler /* 67: SPI3 */
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j UART4_IRQHandler /* 68: UART4 */
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j UART5_IRQHandler /* 69: UART5 */
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j TIM6_IRQHandler /* 70: TIM6 */
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j TIM7_IRQHandler /* 71: TIM7 */
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j DMA2_Channel1_IRQHandler /* 72: DMA2 Channel 1 */
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j DMA2_Channel2_IRQHandler /* 73: DMA2 Channel 2 */
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j DMA2_Channel3_IRQHandler /* 74: DMA2 Channel 3 */
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j DMA2_Channel4_IRQHandler /* 75: DMA2 Channel 4 */
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j DMA2_Channel5_IRQHandler /* 76: DMA2 Channel 5 */
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j ETH_IRQHandler /* 77: ETH */
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j ETH_WKUP_IRQHandler /* 78: ETH WakeUp */
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j CAN2_TX_IRQHandler /* 79: CAN2 TX */
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j CAN2_RX0_IRQHandler /* 80: CAN2 RX0 */
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j CAN2_RX1_IRQHandler /* 81: CAN2 RX1 */
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j CAN2_SCE_IRQHandler /* 82: CAN2 SCE */
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j OTG_FS_IRQHandler /* 83: OTGFS */
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j USBHSWakeup_IRQHandler /* 84: USBHS Wakeup */
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j USBHS_IRQHandler /* 85: USBHS */
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j DVP_IRQHandler /* 86: DVP */
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j UART6_IRQHandler /* 87: UART6 */
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j UART7_IRQHandler /* 88: UART7 */
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j UART8_IRQHandler /* 89: UART8 */
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j TIM9_BRK_IRQHandler /* 90: TIM9 Break */
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j TIM9_UP_IRQHandler /* 91: TIM9 Update */
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j TIM9_TRG_COM_IRQHandler /* 92: TIM9 Trigger and Commutation */
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j TIM9_CC_IRQHandler /* 93: TIM9 Capture Compare */
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j TIM10_BRK_IRQHandler /* 94: TIM10 Break */
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j TIM10_UP_IRQHandler /* 95: TIM10 Update */
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j TIM10_TRG_COM_IRQHandler /* 96: TIM10 Trigger and Commutation */
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j TIM10_CC_IRQHandler /* 97: TIM10 Capture Compare */
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j DMA2_Channel6_IRQHandler /* 98: DMA2 Channel 6 */
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j DMA2_Channel7_IRQHandler /* 99: DMA2 Channel 7 */
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j DMA2_Channel8_IRQHandler /* 100: DMA2 Channel 8 */
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j DMA2_Channel9_IRQHandler /* 101: DMA2 Channel 9 */
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j DMA2_Channel10_IRQHandler /* 102: DMA2 Channel 10 */
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j DMA2_Channel11_IRQHandler /* 103: DMA2 Channel 11 */
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.option pop
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Reset_Handler:
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la sp, _eusrstack
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copy_data:
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/* Load data section from flash to RAM */
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la a0, _sidata
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la a1, _sdata
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la a2, _edata
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bgeu a1, a2, clear_bss
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loop_copy_data:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, loop_copy_data
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clear_bss:
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/* Clear bss section */
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la a0, _sbss
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la a1, _ebss
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bgeu a0, a1, setup_interrupts
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loop_clear_bss:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, loop_clear_bss
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setup_interrupts:
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li t0, 0x1f
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csrw 0xbc0, t0
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/* Enable nested and hardware stack */
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/* li t0, 0x1f */ /* For MRS proprietary GCC compilers */
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/* Enable nested interrupt, disable hardware stack */
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li t0, 0x1e /* Refer to RISC-V4 PFIC manual */
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csrw 0x804, t0
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/* FS: Initial, MPP: M mode, MPIE: EN, MIE: EN */
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li t0, 0x3888
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csrs mstatus, t0
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la t0, _vectors
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ori t0, t0, 0 /* Non-vectored exception handling */
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csrw mtvec, t0 /* Use standard RISC-V exception model. */
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jal SystemInit
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jal main
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dead_loop:
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j dead_loop
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Exception_Handler:
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csrr t0, mcause
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ble t0, x0, Interrupt_Handler /* Check interrupt */
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li t1, 11 /* Find an M mode ecall (11) */
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beq t1, t0, Ecall_M_Handler
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li t1, 8
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beq t1, t0, Ecall_U_Handler
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j Fault_Handler
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Interrupt_Handler: /* Home made vector table */
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slli t0, t0, 2
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la t1, _vectors
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add t1, t1, t0
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jr t1
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