Initial read for Sandisk industrial card.

Signed-off-by: Yilin Sun <imi415@imi.moe>
2023-09-02 16:18:31 +08:00 · 2023-09-02 16:18:31 +08:00 · 3f9d14c39b
parent c492c0d9c8
commit 3f9d14c39b
15 changed files with 1187 additions and 38 deletions
--- a/.drone.yml
+++ b/.drone.yml
@ -14,4 +14,4 @@ steps:
    commands:
      - mkdir build && cd build
      - cmake -DCMAKE_TOOLCHAIN_FILE=arm-none-eabi.cmake ..
-      - make fire_rt1021_evk_template_FLASH.elf
+      - make fire_rt1021_evk_sdsmart_FLASH.elf
--- a/.gitmodules
+++ b/.gitmodules
@ -1,3 +1,6 @@
 [submodule "SDK"]
 	path = SDK
 	url = https://git.minori.work/Embedded_SDK/MCUXpresso_MIMXRT1021xxxxx.git
+[submodule "lib/freertos"]
+	path = lib/freertos
+	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -1,15 +1,18 @@
 cmake_minimum_required(VERSION 3.10)

-project(fire_rt1021_evk_template)
+project(fire_rt1021_evk_sdsmart)

 enable_language(CXX)
 enable_language(ASM)

 # Different linker scripts
-set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1021/gcc/MIMXRT1021xxxxx_flexspi_nor.ld")
+set(TARGET_LDSCRIPT_FLASH "${CMAKE_SOURCE_DIR}/GCC/app_flash.ld")
 set(TARGET_LDSCRIPT_RAM   "${CMAKE_SOURCE_DIR}/SDK/devices/MIMXRT1021/gcc/MIMXRT1021xxxxx_ram.ld")

 set(TARGET_SOURCES
+    "SDK/components/gpio/fsl_adapter_igpio.c"
+    "SDK/components/lists/fsl_component_generic_list.c"
+    "SDK/components/osa/fsl_os_abstraction_free_rtos.c"
    "SDK/components/serial_manager/fsl_component_serial_manager.c"
    "SDK/components/serial_manager/fsl_component_serial_port_uart.c"
    "SDK/components/uart/fsl_adapter_lpuart.c"
@ -85,11 +88,17 @@ set(TARGET_SOURCES
    "SDK/devices/MIMXRT1021/utilities/fsl_notifier.c"
    "SDK/devices/MIMXRT1021/utilities/str/fsl_str.c"
    "SDK/devices/MIMXRT1021/xip/fsl_flexspi_nor_boot.c"
+    "SDK/middleware/sdmmc/common/fsl_sdmmc_common.c"
+    "SDK/middleware/sdmmc/host/usdhc/non_blocking/fsl_sdmmc_host.c"
+    "SDK/middleware/sdmmc/osa/fsl_sdmmc_osa.c"
+    "SDK/middleware/sdmmc/sd/fsl_sd.c"
    "board/board.c"
    "board/clock_config.c"
    "board/dcd.c"
    "board/peripherals.c"
    "board/pin_mux.c"
+    "board/sdmmc_config.c"
+    "src/app_sdmmc.c"
    "src/main.c"
    "xip/fire_rt1021_evk_flexspi_nor_config.c"
 )
@ -97,6 +106,8 @@ set(TARGET_SOURCES
 set(TARGET_C_DEFINES
    "CPU_MIMXRT1021DAG5A"
    "MCUXPRESSO_SDK"
+    "SD_ENABLED"
+    "SDK_OS_FREE_RTOS"
    "SERIAL_PORT_TYPE_UART"
    "__STARTUP_CLEAR_BSS"
    "__STARTUP_INITIALIZE_NONCACHEDATA"
@ -111,6 +122,9 @@ set(TARGET_C_DEFINES_XIP

 set(TARGET_C_INCLUDES
    "SDK/CMSIS/Core/Include"
+    "SDK/components/gpio"
+    "SDK/components/lists"
+    "SDK/components/osa"
    "SDK/components/serial_manager"
    "SDK/components/uart"
    "SDK/devices/MIMXRT1021"
@ -118,6 +132,10 @@ set(TARGET_C_INCLUDES
    "SDK/devices/MIMXRT1021/utilities"
    "SDK/devices/MIMXRT1021/utilities/debug_console"
    "SDK/devices/MIMXRT1021/utilities/str"
+    "SDK/middleware/sdmmc/common"
+    "SDK/middleware/sdmmc/host/usdhc"
+    "SDK/middleware/sdmmc/osa"
+    "SDK/middleware/sdmmc/sd"
    "board"
    "include"
 )
@ -127,6 +145,7 @@ set(TARGET_LIBS
    "c"
    "m"
    "nosys"
+    "freertos_kernel"
 )

 # Shared library and linker script search paths
@ -152,6 +171,12 @@ set(CMAKE_CXX_FLAGS        "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -f
 set(CMAKE_ASM_FLAGS        "${CMAKE_C_FLAGS} -x assembler-with-cpp")
 set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections")

+# Subdirectories
+set(FREERTOS_PORT "GCC_ARM_CM7" CACHE STRING "")
+add_library(freertos_config INTERFACE)
+target_include_directories(freertos_config SYSTEM INTERFACE include)
+add_subdirectory(lib/freertos)
+
 # Shared sources, includes and definitions
 add_compile_definitions(${TARGET_C_DEFINES})
 include_directories(${TARGET_C_INCLUDES})
--- a/GCC/app_flash.ld
+++ b/GCC/app_flash.ld
@ -0,0 +1,278 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1021CAF4A
+**                          MIMXRT1021CAG4A
+**                          MIMXRT1021DAF5A
+**                          MIMXRT1021DAG5A
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
+**     Version:             rev. 0.1, 2017-06-06
+**     Build:               b210709
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2021 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_flash_config        (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
+  m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
+  m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x01FFDC00
+  m_qacode              (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00010000
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00010000
+  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00020000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  __NCACHE_REGION_START = ORIGIN(m_data2);
+  __NCACHE_REGION_SIZE  = 0;
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    __FLASH_BASE = .;
+    KEEP(* (.boot_hdr.conf))     /* flash config section */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
+
+  .ivt : AT(ivt_begin)
+  {
+    . = ALIGN(4);
+    KEEP(* (.boot_hdr.ivt))           /* ivt section */
+    KEEP(* (.boot_hdr.boot_data))     /* boot section */
+    KEEP(* (.boot_hdr.dcd_data))      /* dcd section */
+    . = ALIGN(4);
+  } > m_ivt
+
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    __Vectors = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(m_usb_dma_init_data)
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    *(DataQuickAccess)       /* quick access data section */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
+
+  .ram_function : AT(__ram_function_flash_start)
+  {
+    . = ALIGN(32);
+    __ram_function_start__ = .;
+    *(CodeQuickAccess)
+    . = ALIGN(128);
+    __ram_function_end__ = .;
+  } > m_qacode
+
+  __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
+  .ncache.init : AT(__NDATA_ROM)
+  {
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
+    . = ALIGN(4);
+    __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
+  } > m_data
+  . = __noncachedata_init_end__;
+  .ncache :
+  {
+    *(NonCacheable)
+    . = ALIGN(4);
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+  } > m_data
+
+  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(m_usb_dma_noninit_data)
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  .freertos_heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    *(.freertos_heap)
+    *(.freertos_heap*)
+  } > m_data2
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
--- a/MIMXRT1021xxxxx.mex
+++ b/MIMXRT1021xxxxx.mex
@ -24,6 +24,12 @@
         </generated_project_files>
         <pins_profile>
            <processor_version>14.0.0</processor_version>
+            <pin_labels>
+               <pin_label pin_num="76" pin_signal="GPIO_AD_B1_13" label="IND" identifier="LED_IND;IND"/>
+               <pin_label pin_num="82" pin_signal="GPIO_AD_B1_08" label="R" identifier="R"/>
+               <pin_label pin_num="81" pin_signal="GPIO_AD_B1_09" label="G" identifier="G"/>
+               <pin_label pin_num="80" pin_signal="GPIO_AD_B1_10" label="B" identifier="B"/>
+            </pin_labels>
            <power_domains>
               <power_domain name="NVCC_GPIO" value="3.3"/>
            </power_domains>
@ -54,8 +60,102 @@
                  </dependency>
               </dependencies>
               <pins>
-                  <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
                  <pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
+               </pins>
+            </function>
+            <function name="BOARD_InituSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InituSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InituSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InituSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_reset_b" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO1" signal="gpio_io, 29" pin_num="76" pin_signal="GPIO_AD_B1_13">
+                     <pin_features>
+                        <pin_feature name="identifier" value="IND"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_50"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 24" pin_num="82" pin_signal="GPIO_AD_B1_08">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_50"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 25" pin_num="81" pin_signal="GPIO_AD_B1_09">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_50"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 26" pin_num="80" pin_signal="GPIO_AD_B1_10">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_50"/>
+                     </pin_features>
+                  </pin>
               </pins>
            </function>
         </functions_list>
--- a/1
+++ b/1
@ -0,0 +1 @@
+Subproject commit ec9dcda9ee2f229b64090ab0ccf11e4015c5770a
--- a/board/pin_mux.c
+++ b/board/pin_mux.c
@ -11,12 +11,18 @@ processor: MIMXRT1021xxxxx
 package_id: MIMXRT1021DAG5A
 mcu_data: ksdk2_0
 processor_version: 14.0.0
+pin_labels:
+- {pin_num: '76', pin_signal: GPIO_AD_B1_13, label: IND, identifier: LED_IND;IND}
+- {pin_num: '82', pin_signal: GPIO_AD_B1_08, label: R, identifier: R}
+- {pin_num: '81', pin_signal: GPIO_AD_B1_09, label: G, identifier: G}
+- {pin_num: '80', pin_signal: GPIO_AD_B1_10, label: B, identifier: B}
 power_domains: {NVCC_GPIO: '3.3'}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
 */

 #include "fsl_common.h"
 #include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
 #include "pin_mux.h"

 /* FUNCTION ************************************************************************************************************
@ -27,6 +33,8 @@ power_domains: {NVCC_GPIO: '3.3'}
 * END ****************************************************************************************************************/
 void BOARD_InitBootPins(void) {
    BOARD_InitDbgUARTPins();
+    BOARD_InituSDHCPins();
+    BOARD_InitLEDPins();
 }

 /*
@ -34,8 +42,8 @@ void BOARD_InitBootPins(void) {
 BOARD_InitDbgUARTPins:
 - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
 - pin_list:
-  - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
  - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
+  - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
 */

@ -52,6 +60,109 @@ void BOARD_InitDbgUARTPins(void) {
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); 
 }

+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InituSDHCPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '45', peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_03}
+  - {pin_num: '46', peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_02}
+  - {pin_num: '43', peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_04}
+  - {pin_num: '42', peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_05}
+  - {pin_num: '48', peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_00}
+  - {pin_num: '47', peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_01}
+  - {pin_num: '41', peripheral: USDHC1, signal: usdhc_reset_b, pin_signal: GPIO_SD_B0_06}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InituSDHCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InituSDHCPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_CMD, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_CLK, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B, 0U); 
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLEDPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '76', peripheral: GPIO1, signal: 'gpio_io, 29', pin_signal: GPIO_AD_B1_13, identifier: IND, direction: OUTPUT, gpio_init_state: 'true', open_drain: Enable,
+    speed: MHZ_50}
+  - {pin_num: '82', peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08, direction: OUTPUT, gpio_init_state: 'true', open_drain: Enable, speed: MHZ_50}
+  - {pin_num: '81', peripheral: GPIO1, signal: 'gpio_io, 25', pin_signal: GPIO_AD_B1_09, direction: OUTPUT, gpio_init_state: 'true', open_drain: Enable, speed: MHZ_50}
+  - {pin_num: '80', peripheral: GPIO1, signal: 'gpio_io, 26', pin_signal: GPIO_AD_B1_10, direction: OUTPUT, gpio_init_state: 'true', open_drain: Enable, speed: MHZ_50}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLEDPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLEDPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           
+
+  /* GPIO configuration of R on GPIO_AD_B1_08 (pin 82) */
+  gpio_pin_config_t R_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 1U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B1_08 (pin 82) */
+  GPIO_PinInit(GPIO1, 24U, &R_config);
+
+  /* GPIO configuration of G on GPIO_AD_B1_09 (pin 81) */
+  gpio_pin_config_t G_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 1U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B1_09 (pin 81) */
+  GPIO_PinInit(GPIO1, 25U, &G_config);
+
+  /* GPIO configuration of B on GPIO_AD_B1_10 (pin 80) */
+  gpio_pin_config_t B_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 1U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B1_10 (pin 80) */
+  GPIO_PinInit(GPIO1, 26U, &B_config);
+
+  /* GPIO configuration of IND on GPIO_AD_B1_13 (pin 76) */
+  gpio_pin_config_t IND_config = {
+      .direction = kGPIO_DigitalOutput,
+      .outputLogic = 1U,
+      .interruptMode = kGPIO_NoIntmode
+  };
+  /* Initialize GPIO functionality on GPIO_AD_B1_13 (pin 76) */
+  GPIO_PinInit(GPIO1, 29U, &IND_config);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_GPIO1_IO26, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, 0U); 
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, 0x1830U); 
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, 0x1830U); 
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_10_GPIO1_IO26, 0x1830U); 
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, 0x1830U); 
+}
+
 /***********************************************************************************************************************
 * EOF
 **********************************************************************************************************************/
--- a/board/pin_mux.h
+++ b/board/pin_mux.h
@ -44,6 +44,76 @@ void BOARD_InitBootPins(void);
 */
 void BOARD_InitDbgUARTPins(void);

+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InituSDHCPins(void);
+
+/* GPIO_AD_B1_13 (number 76), IND */
+/* Routed pin properties */
+#define BOARD_INITLEDPINS_IND_PERIPHERAL                                   GPIO1   /*!< Peripheral name */
+#define BOARD_INITLEDPINS_IND_SIGNAL                                     gpio_io   /*!< Signal name */
+#define BOARD_INITLEDPINS_IND_CHANNEL                                        29U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDPINS_IND_GPIO                                         GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITLEDPINS_IND_GPIO_PIN                                       29U   /*!< GPIO pin number */
+#define BOARD_INITLEDPINS_IND_GPIO_PIN_MASK                          (1U << 29U)   /*!< GPIO pin mask */
+#define BOARD_INITLEDPINS_IND_PORT                                         GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITLEDPINS_IND_PIN                                            29U   /*!< PORT pin number */
+#define BOARD_INITLEDPINS_IND_PIN_MASK                               (1U << 29U)   /*!< PORT pin mask */
+
+/* GPIO_AD_B1_08 (number 82), R */
+/* Routed pin properties */
+#define BOARD_INITLEDPINS_R_PERIPHERAL                                     GPIO1   /*!< Peripheral name */
+#define BOARD_INITLEDPINS_R_SIGNAL                                       gpio_io   /*!< Signal name */
+#define BOARD_INITLEDPINS_R_CHANNEL                                          24U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDPINS_R_GPIO                                           GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITLEDPINS_R_GPIO_PIN                                         24U   /*!< GPIO pin number */
+#define BOARD_INITLEDPINS_R_GPIO_PIN_MASK                            (1U << 24U)   /*!< GPIO pin mask */
+#define BOARD_INITLEDPINS_R_PORT                                           GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITLEDPINS_R_PIN                                              24U   /*!< PORT pin number */
+#define BOARD_INITLEDPINS_R_PIN_MASK                                 (1U << 24U)   /*!< PORT pin mask */
+
+/* GPIO_AD_B1_09 (number 81), G */
+/* Routed pin properties */
+#define BOARD_INITLEDPINS_G_PERIPHERAL                                     GPIO1   /*!< Peripheral name */
+#define BOARD_INITLEDPINS_G_SIGNAL                                       gpio_io   /*!< Signal name */
+#define BOARD_INITLEDPINS_G_CHANNEL                                          25U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDPINS_G_GPIO                                           GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITLEDPINS_G_GPIO_PIN                                         25U   /*!< GPIO pin number */
+#define BOARD_INITLEDPINS_G_GPIO_PIN_MASK                            (1U << 25U)   /*!< GPIO pin mask */
+#define BOARD_INITLEDPINS_G_PORT                                           GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITLEDPINS_G_PIN                                              25U   /*!< PORT pin number */
+#define BOARD_INITLEDPINS_G_PIN_MASK                                 (1U << 25U)   /*!< PORT pin mask */
+
+/* GPIO_AD_B1_10 (number 80), B */
+/* Routed pin properties */
+#define BOARD_INITLEDPINS_B_PERIPHERAL                                     GPIO1   /*!< Peripheral name */
+#define BOARD_INITLEDPINS_B_SIGNAL                                       gpio_io   /*!< Signal name */
+#define BOARD_INITLEDPINS_B_CHANNEL                                          26U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDPINS_B_GPIO                                           GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITLEDPINS_B_GPIO_PIN                                         26U   /*!< GPIO pin number */
+#define BOARD_INITLEDPINS_B_GPIO_PIN_MASK                            (1U << 26U)   /*!< GPIO pin mask */
+#define BOARD_INITLEDPINS_B_PORT                                           GPIO1   /*!< PORT peripheral base pointer */
+#define BOARD_INITLEDPINS_B_PIN                                              26U   /*!< PORT pin number */
+#define BOARD_INITLEDPINS_B_PIN_MASK                                 (1U << 26U)   /*!< PORT pin mask */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLEDPins(void);
+
 #if defined(__cplusplus)
 }
 #endif
--- a/board/sdmmc_config.c
+++ b/board/sdmmc_config.c
@ -0,0 +1,194 @@
+/*
+ * Copyright 2020-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "sdmmc_config.h"
+
+#include "fsl_iomuxc.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void BOARD_SDCardPowerControl(bool enable);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*!brief sdmmc dma buffer */
+AT_NONCACHEABLE_SECTION_ALIGN(static uint32_t s_sdmmcHostDmaBuffer[BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE],
+                              SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE);
+#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
+/* two cache line length for sdmmc host driver maintain unalign transfer */
+SDK_ALIGN(static uint8_t s_sdmmcCacheLineAlignBuffer[BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U],
+          BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE);
+#endif
+#if defined(SDIO_ENABLED) || defined(SD_ENABLED)
+static sd_detect_card_t s_cd;
+static sd_io_voltage_t  s_ioVoltage = {
+     .type = BOARD_SDMMC_SD_IO_VOLTAGE_CONTROL_TYPE,
+     .func = NULL,
+};
+#endif
+static sdmmchost_t s_host;
+
+#ifdef SDIO_ENABLED
+static sdio_card_int_t s_sdioInt;
+#endif
+
+GPIO_HANDLE_DEFINE(s_CardDetectGpioHandle);
+GPIO_HANDLE_DEFINE(s_PowerResetGpioHandle);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+uint32_t BOARD_USDHC1ClockConfiguration(void) {
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClock500MHz);
+    /*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
+    /* Configure USDHC clock source and divider */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); /* USDHC clock root frequency maximum: 198MHZ */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
+
+    return 396000000U / 2U;
+}
+
+#if defined(SDIO_ENABLED) || defined(SD_ENABLED)
+bool BOARD_SDCardGetDetectStatus(void) {
+    uint8_t pinState;
+
+    if (HAL_GpioGetInput(s_CardDetectGpioHandle, &pinState) == kStatus_HAL_GpioSuccess) {
+        if (pinState == BOARD_SDMMC_SD_CD_INSERT_LEVEL) {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+void BOARD_SDCardDAT3PullFunction(uint32_t status) {
+    if (status == kSD_DAT3PullDown) {
+        IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3,
+                            IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                                IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                                IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
+                                IOMUXC_SW_PAD_CTL_PAD_DSE(1));
+    } else {
+        IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3,
+                            IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                                IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                                IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                                IOMUXC_SW_PAD_CTL_PAD_DSE(1));
+    }
+}
+
+void BOARD_SDCardDetectInit(sd_cd_t cd, void *userData) {
+    /* install card detect callback */
+    s_cd.cdDebounce_ms = BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS;
+    s_cd.type          = BOARD_SDMMC_SD_CD_TYPE;
+    s_cd.cardDetected  = BOARD_SDCardGetDetectStatus;
+    s_cd.callback      = cd;
+    s_cd.userData      = userData;
+
+    s_cd.dat3PullFunc = BOARD_SDCardDAT3PullFunction;
+    /* make sure the card is power on for DAT3 pull up */
+    BOARD_SDCardPowerControl(true);
+}
+
+void BOARD_SDCardPowerResetInit(void) {
+    hal_gpio_pin_config_t sw_config = {
+        kHAL_GpioDirectionOut,
+        0,
+        BOARD_SDMMC_SD_POWER_RESET_GPIO_PORT,
+        BOARD_SDMMC_SD_POWER_RESET_GPIO_PIN,
+    };
+    HAL_GpioInit(s_PowerResetGpioHandle, &sw_config);
+}
+
+void BOARD_SDCardPowerControl(bool enable) {
+    if (enable) {
+        USDHC_AssertHardwareReset(BOARD_SDMMC_SD_HOST_BASEADDR, true);
+    } else {
+        USDHC_AssertHardwareReset(BOARD_SDMMC_SD_HOST_BASEADDR, false);
+    }
+}
+
+void BOARD_SD_Pin_Config(uint32_t freq) {
+    uint32_t speed = 0U, strength = 0U;
+
+    if (freq <= 50000000) {
+        speed    = 0U;
+        strength = 7U;
+    } else if (freq <= 100000000) {
+        speed    = 2U;
+        strength = 7U;
+    } else {
+        speed    = 3U;
+        strength = 7U;
+    }
+
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_CMD,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_CLK,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+}
+#endif
+
+#if defined(SD_ENABLED)
+void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData) {
+    assert(card);
+
+    s_host.dmaDesBuffer         = s_sdmmcHostDmaBuffer;
+    s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE;
+    s_host.enableCacheControl   = BOARD_SDMMC_HOST_CACHE_CONTROL;
+#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
+    s_host.cacheAlignBuffer     = s_sdmmcCacheLineAlignBuffer;
+    s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
+#endif
+
+    ((sd_card_t *)card)->host                                = &s_host;
+    ((sd_card_t *)card)->host->hostController.base           = BOARD_SDMMC_SD_HOST_BASEADDR;
+    ((sd_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration();
+
+    ((sd_card_t *)card)->usrParam.cd         = &s_cd;
+    ((sd_card_t *)card)->usrParam.pwr        = BOARD_SDCardPowerControl;
+    ((sd_card_t *)card)->usrParam.ioStrength = BOARD_SD_Pin_Config;
+    ((sd_card_t *)card)->usrParam.ioVoltage  = &s_ioVoltage;
+    ((sd_card_t *)card)->usrParam.maxFreq    = BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ;
+
+    BOARD_SDCardPowerResetInit();
+    BOARD_SDCardDetectInit(cd, userData);
+
+    NVIC_SetPriority(BOARD_SDMMC_SD_HOST_IRQ, hostIRQPriority);
+}
+#endif
--- a/board/sdmmc_config.h
+++ b/board/sdmmc_config.h
@ -0,0 +1,114 @@
+/*
+* Copyright 2020-2022 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef _SDMMC_CONFIG_H_
+#define _SDMMC_CONFIG_H_
+
+#ifdef SD_ENABLED
+#include "fsl_sd.h"
+#endif
+#ifdef MMC_ENABLED
+#include "fsl_mmc.h"
+#endif
+#ifdef SDIO_ENABLED
+#include "fsl_sdio.h"
+#endif
+#include "clock_config.h"
+#include "fsl_adapter_gpio.h"
+#include "fsl_sdmmc_host.h"
+#include "fsl_sdmmc_common.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/* @brief host basic configuration */
+#define BOARD_SDMMC_SD_HOST_BASEADDR   USDHC1
+#define BOARD_SDMMC_SD_HOST_IRQ        USDHC1_IRQn
+#define BOARD_SDMMC_MMC_HOST_BASEADDR  USDHC1
+#define BOARD_SDMMC_MMC_HOST_IRQ       USDHC1_IRQn
+#define BOARD_SDMMC_SDIO_HOST_BASEADDR USDHC1
+#define BOARD_SDMMC_SDIO_HOST_IRQ      USDHC1_IRQn
+/* @brief card detect configuration */
+#define BOARD_SDMMC_SD_CD_GPIO_BASE      GPIO3
+#define BOARD_SDMMC_SD_CD_GPIO_PORT      3
+#define BOARD_SDMMC_SD_CD_GPIO_PIN       19U
+#define BOARD_SDMMC_SD_CD_INTTERUPT_TYPE kHAL_GpioInterruptEitherEdge
+#define BOARD_SDMMC_SD_CD_INSERT_LEVEL   (0U)
+/* @brief card detect type
+*
+* Note: Please pay attention, DAT3 card detection cannot work during the card access,
+* since the DAT3 will be used for data transfer, thus the functionality of card detect will be disabled. Using card
+* detect pin for card detection is recommended.
+*/
+#define BOARD_SDMMC_SD_CD_TYPE                       kSD_DetectCardByHostDATA3
+#define BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS (100U)
+/*! @brief SD power reset */
+#define BOARD_SDMMC_SD_POWER_RESET_GPIO_BASE GPIO3
+#define BOARD_SDMMC_SD_POWER_RESET_GPIO_PORT 3
+#define BOARD_SDMMC_SD_POWER_RESET_GPIO_PIN  24U
+/*! @brief SD IO voltage */
+#define BOARD_SDMMC_SD_IO_VOLTAGE_CONTROL_TYPE kSD_IOVoltageCtrlNotSupport
+
+#define BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ (100000000U)
+#define BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ (180000000U)
+
+/* @brief mmc configuration */
+#define BOARD_SDMMC_MMC_VCC_SUPPLY  kMMC_VoltageWindows270to360
+#define BOARD_SDMMC_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360
+/*! @brief align with cache line size */
+#define BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE (32U)
+/*!@ brief host interrupt priority*/
+#define BOARD_SDMMC_SD_HOST_IRQ_PRIORITY   (5U)
+#define BOARD_SDMMC_MMC_HOST_IRQ_PRIORITY  (5U)
+#define BOARD_SDMMC_SDIO_HOST_IRQ_PRIORITY (5U)
+/*!@brief dma descriptor buffer size */
+#define BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE (32U)
+/*! @brief cache maintain function enabled for RW buffer */
+#define BOARD_SDMMC_HOST_CACHE_CONTROL kSDMMCHOST_CacheControlRWBuffer
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+* API
+******************************************************************************/
+/*!
+* @brief BOARD SD configurations.
+* @param card card descriptor
+* @param cd card detect callback
+* @param userData user data for callback
+*/
+#ifdef SD_ENABLED
+void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData);
+#endif
+
+/*!
+* @brief BOARD SDIO configurations.
+* @param card card descriptor
+* @param cd card detect callback
+* @param cardInt card interrupt
+*/
+#ifdef SDIO_ENABLED
+void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt);
+#endif
+
+/*!
+* @brief BOARD MMC configurations.
+* @param card card descriptor
+* @param cd card detect callback
+* @param userData user data for callback
+*/
+#ifdef MMC_ENABLED
+void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
--- a/include/FreeRTOSConfig.h
+++ b/include/FreeRTOSConfig.h
@ -0,0 +1,116 @@
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_TICKLESS_IDLE                 0
+#define configCPU_CLOCK_HZ                      (SystemCoreClock)
+#define configTICK_RATE_HZ                      ((TickType_t)250)
+#define configMAX_PRIORITIES                    5
+#define configMINIMAL_STACK_SIZE                ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN                 20
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_TASK_NOTIFICATIONS            1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configUSE_ALTERNATIVE_API               0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE               8
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+#define configTOTAL_HEAP_SIZE                   ((size_t)(124 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                     0
+#define configUSE_TICK_HOOK                     0
+#define configCHECK_FOR_STACK_OVERFLOW          0
+#define configUSE_MALLOC_FAILED_HOOK            0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK      0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_TRACE_FACILITY                1
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS         1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES                   0
+#define configMAX_CO_ROUTINE_PRIORITIES         2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                        1
+#define configTIMER_TASK_PRIORITY               (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH                10
+#define configTIMER_TASK_STACK_DEPTH            (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet                1
+#define INCLUDE_uxTaskPriorityGet               1
+#define INCLUDE_vTaskDelete                     1
+#define INCLUDE_vTaskSuspend                    1
+#define INCLUDE_vTaskDelayUntil                 1
+#define INCLUDE_vTaskDelay                      1
+#define INCLUDE_xTaskGetSchedulerState          1
+#define INCLUDE_xTaskGetCurrentTaskHandle       1
+#define INCLUDE_uxTaskGetStackHighWaterMark     0
+#define INCLUDE_xTaskGetIdleTaskHandle          0
+#define INCLUDE_eTaskGetState                   0
+#define INCLUDE_xTimerPendFunctionCall          1
+#define INCLUDE_xTaskAbortDelay                 0
+#define INCLUDE_xTaskGetHandle                  0
+#define INCLUDE_xTaskResumeFromISR              1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+/* Clock manager provides in this variable system core clock frequency */
+#include <stdint.h>
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
--- a/include/app_sdmmc.h
+++ b/include/app_sdmmc.h
@ -0,0 +1,6 @@
+#ifndef APP_SDMMC_H
+#define APP_SDMMC_H
+
+int app_sdmmc_init(void);
+
+#endif  // APP_SDMMC_H
--- a/lib/freertos
+++ b/lib/freertos
@ -0,0 +1 @@
+Subproject commit 0264280230aa6a828247b5f05bf57e33f1994581
--- a/src/app_sdmmc.c
+++ b/src/app_sdmmc.c
@ -0,0 +1,121 @@
+/* Debug Console */
+#include "fsl_debug_console.h"
+
+/* FreeRTOS */
+#include "FreeRTOS.h"
+#include "event_groups.h"
+#include "queue.h"
+#include "semphr.h"
+#include "task.h"
+
+/* SDMMC */
+#include "sdmmc_config.h"
+
+/* Private */
+#include "app_sdmmc.h"
+
+static sd_card_t s_app_sd;
+static SDK_ALIGN(uint8_t s_data_buffer[512], BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE);
+
+typedef struct __attribute__((packed)) {
+    uint16_t sd_identifier;
+    uint8_t  mfg_date[6];
+    uint8_t  health_status;
+    uint16_t feature_revision;
+    uint16_t generation_identifier;
+} sandisk_status_t;
+
+static void app_sdmmc_task(void *parameters);
+
+int app_sdmmc_init(void) {
+    if (xTaskCreate(app_sdmmc_task, "SDMMC", 1024, NULL, 4, NULL) != pdPASS) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static void app_sdmmc_detected(bool inserted, void *user_data) {
+    QueueHandle_t cd_q = user_data;
+
+    BaseType_t higher_prio_woken = pdFALSE;
+    xQueueSendFromISR(cd_q, &inserted, &higher_prio_woken);
+
+    portYIELD_FROM_ISR(higher_prio_woken);
+}
+
+static void app_sdmmc_task(void *parameters) {
+    QueueHandle_t cd_q = xQueueCreate(1, sizeof(bool));
+    if (cd_q == NULL) {
+        PRINTF("Failed to create card detection queue.\r\n");
+
+        vTaskDelete(NULL);
+    }
+
+    BOARD_SD_Config(&s_app_sd, app_sdmmc_detected, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY, cd_q);
+    if (SD_HostInit(&s_app_sd) != kStatus_Success) {
+        PRINTF("Failed to initialize SD host.\r\n");
+
+        vTaskDelete(NULL);
+    }
+
+    for (;;) {
+        bool inserted = false;
+        if (xQueueReceive(cd_q, &inserted, portMAX_DELAY) != pdFALSE) {
+            if (inserted) {
+                PRINTF("SD card inserted.\r\n");
+
+                /* Reset card */
+                SD_SetCardPower(&s_app_sd, false);
+                SD_SetCardPower(&s_app_sd, true);
+
+                if (SD_CardInit(&s_app_sd) != kStatus_Success) {
+                    PRINTF("Failed to initialize SD card.\r\n");
+                    vTaskDelete(NULL);
+                }
+
+                PRINTF("Card MID: %02x\r\n", s_app_sd.cid.manufacturerID);
+                PRINTF("Card AID: %04x\r\n", s_app_sd.cid.applicationID);
+
+                /* Sandisk */
+                if (s_app_sd.cid.manufacturerID == 3) {
+                    sdmmchost_transfer_t content = {0};
+                    sdmmchost_cmd_t      command = {0};
+                    sdmmchost_data_t     data    = {0};
+
+                    memset(&data, 0x00, sizeof(data));
+
+                    command.index        = kSDMMC_GeneralCommand;
+                    command.argument     = 0x01;
+                    command.responseType = kCARD_ResponseTypeR1;
+
+                    data.blockSize  = 512U;
+                    data.blockCount = 1U;
+                    data.rxData     = (uint32_t *)s_data_buffer;
+
+                    content.command = &command;
+                    content.data    = &data;
+
+                    if (SDMMCHOST_TransferFunction(s_app_sd.host, &content) != kStatus_Success) {
+                        PRINTF("Failed to send CMD56\r\n");
+
+                        vTaskDelete(NULL);
+                    }
+
+                    PRINTF("GEN_CMD sent.\r\n");
+
+                    if (command.response[0] & SDMMC_R1_ALL_ERROR_FLAG) {
+                        PRINTF("SD card reported error.\r\n");
+                    }
+
+                    sandisk_status_t *st = (sandisk_status_t *)s_data_buffer;
+
+                    PRINTF("ID: %04x\r\n", st->sd_identifier);
+                }
+
+            } else {
+                PRINTF("SD card removed.\r\n");
+            }
+        }
+    }
+}
--- a/src/main.c
+++ b/src/main.c
@ -1,47 +1,56 @@
-/*
- * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_device_registers.h"
-#include "fsl_debug_console.h"
-#include "pin_mux.h"
-#include "clock_config.h"
+/* Board */
 #include "board.h"
+#include "clock_config.h"
+#include "pin_mux.h"

-/*******************************************************************************
- * Definitions
- ******************************************************************************/
+/* Debug Console */
+#include "fsl_debug_console.h"

+/* FreeRTOS */
+#include "FreeRTOS.h"
+#include "task.h"

-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
+/* App */
+#include "app_sdmmc.h"

-/*******************************************************************************
- * Code
- ******************************************************************************/
-/*!
- * @brief Main function
- */
-int main(void)
-{
-    char ch;
+/* FreeRTOS heap placed into DTCM */
+__attribute__((section(".freertos_heap"))) uint8_t ucHeap[configTOTAL_HEAP_SIZE];

-    /* Init board hardware. */
+static void init_task(void *parameters);
+
+int main(void) {
    BOARD_ConfigMPU();
    BOARD_InitBootPins();
    BOARD_InitBootClocks();
    BOARD_InitDebugConsole();

-    PRINTF("hello world.\r\n");
+    if (xTaskCreate(init_task, "INIT", 1024, NULL, 4, NULL) != pdPASS) {
+        PRINTF("Failed to create init task.\r\n");

-    while (1)
-    {
-        ch = GETCHAR();
-        PUTCHAR(ch);
+        goto dead_loop;
+    }
+
+    vTaskStartScheduler();
+
+dead_loop:
+    for (;;) {
+        __WFI();
    }
 }
+
+static void init_task(void *parameters) {
+    PRINTF("Initialization task running...\r\n");
+
+    if (app_sdmmc_init() != 0) {
+        PRINTF("Failed to initialize SDMMC.\r\n");
+    }
+
+    for (;;) {
+        GPIO_PinWrite(BOARD_INITLEDPINS_IND_GPIO, BOARD_INITLEDPINS_IND_PIN, 0U);
+        vTaskDelay(pdMS_TO_TICKS(500));
+        GPIO_PinWrite(BOARD_INITLEDPINS_IND_GPIO, BOARD_INITLEDPINS_IND_PIN, 1U);
+        vTaskDelay(pdMS_TO_TICKS(500));
+    }
+
+    vTaskDelete(NULL);
+}
				`@ -0,0 +1 @@`
				`Subproject commit ec9dcda9ee2f229b64090ab0ccf11e4015c5770a`
				`@ -0,0 +1 @@`
				`Subproject commit 0264280230aa6a828247b5f05bf57e33f1994581`