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Updated clock options and LED GPIO groups.

This commit is contained in:
imi415 2022-08-26 23:34:28 +08:00
parent daf4d9d699
commit 733eaad9f8
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
10 changed files with 1205 additions and 893 deletions
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203
MIMXRT1052xxxxB.mex
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1052xxxxB" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_11 http://mcuxpresso.nxp.com/XSD/mex_configuration_11.xsd" uuid="ea584181-55b7-4bac-96ba-c53df188dbf3" version="11" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_11" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<configuration name="MIMXRT1052xxxxB" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_12 http://mcuxpresso.nxp.com/XSD/mex_configuration_12.xsd" uuid="ea584181-55b7-4bac-96ba-c53df188dbf3" version="12" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_12" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1052xxxxB</processor>
<package>MIMXRT1052DVL6B</package>
@ -17,22 +17,22 @@
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="11.0" enabled="true" update_project_code="true">
<pins name="Pins" version="12.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>11.0.1</processor_version>
<power_domains/>
<processor_version>12.0.0</processor_version>
<pin_labels>
<pin_label pin_num="C7" pin_signal="GPIO_EMC_41" label="LED_B" identifier="LED_R;LED_B"/>
<pin_label pin_num="B12" pin_signal="GPIO_B1_07" label="LED_G" identifier="LED_G"/>
<pin_label pin_num="A7" pin_signal="GPIO_EMC_40" label="LED_R" identifier="LED_B;LED_R"/>
</pin_labels>
<power_domains/>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<function name="BOARD_InitDbgConsolePins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
@ -40,22 +40,17 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDbgConsolePins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDbgConsolePins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDbgConsolePins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
@ -64,6 +59,33 @@
<pins>
<pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12"/>
<pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13"/>
</pins>
</function>
<function name="BOARD_InitLEDPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO3" signal="gpio_io, 27" pin_num="C7" pin_signal="GPIO_EMC_41">
<pin_features>
<pin_feature name="identifier" value="LED_B"/>
@ -88,45 +110,45 @@
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="9.0" enabled="true" update_project_code="true">
<clocks name="Clocks" version="10.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>11.0.1</processor_version>
<processor_version>12.0.0</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<clock_configuration name="Board_BootClockPLL600MHz" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:Board_BootClockPLL600MHz">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:Board_BootClockPLL600MHz">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:Board_BootClockPLL600MHz">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:Board_BootClockPLL600MHz">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:Board_BootClockPLL600MHz">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:Board_BootClockPLL600MHz">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
@ -134,7 +156,7 @@
</dependencies>
<clock_sources/>
<clock_outputs>
<clock_output id="AHB_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
<clock_output id="CAN_CLK_ROOT.outFreq" value="2 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
@ -143,16 +165,16 @@
<clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="2 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
<clock_output id="LCDIF_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="LVDS1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="5 MHz" locked="false" accuracy=""/>
<clock_output id="PLL7_MAIN_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="3 MHz" locked="false" accuracy=""/>
@ -164,39 +186,53 @@
<clock_output id="SAI3_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="4 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="88 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="4 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="1" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
<setting id="CCM.PERCLK_PODF.scale" value="30" locked="false"/>
<setting id="CCM.SEMC_CLK_SEL.sel" value="CCM.SEMC_ALT_CLK_SEL" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="3" locked="true"/>
<setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
<setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
<setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
</clock_settings>
<called_from_default_init>false</called_from_default_init>
</clock_configuration>
<clock_configuration name="Board_BootClock600MHz" id_prefix="" prefix_user_defined="false">
<clock_configuration name="Board_BootClockPLL480MHz" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:Board_BootClock600MHz">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:Board_BootClockPLL480MHz">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:Board_BootClock600MHz">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:Board_BootClockPLL480MHz">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:Board_BootClock600MHz">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:Board_BootClockPLL480MHz">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:Board_BootClock600MHz">
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:Board_BootClockPLL480MHz">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
@ -204,7 +240,7 @@
</dependencies>
<clock_sources/>
<clock_outputs>
<clock_output id="AHB_CLK_ROOT.outFreq" value="528 MHz" locked="false" accuracy=""/>
<clock_output id="AHB_CLK_ROOT.outFreq" value="480 MHz" locked="false" accuracy=""/>
<clock_output id="CAN_CLK_ROOT.outFreq" value="2 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
@ -216,11 +252,11 @@
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="4 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="4 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="LCDIF_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="LVDS1_CLK.outFreq" value="1.056 GHz" locked="false" accuracy=""/>
<clock_output id="LVDS1_CLK.outFreq" value="960 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="4 MHz" locked="false" accuracy=""/>
<clock_output id="PLL7_MAIN_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
@ -245,12 +281,12 @@
<setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="1" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
<setting id="CCM.PERCLK_PODF.scale" value="33" locked="false"/>
<setting id="CCM.PERCLK_PODF.scale" value="30" locked="false"/>
<setting id="CCM.SEMC_CLK_SEL.sel" value="CCM.SEMC_ALT_CLK_SEL" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="3" locked="true"/>
<setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
<setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
<setting id="CCM_ANALOG.PLL1_VDIV.scale" value="44" locked="true"/>
<setting id="CCM_ANALOG.PLL1_VDIV.scale" value="40" locked="true"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
@ -261,6 +297,81 @@
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
<clock_configuration name="BOARD_BootClockXT24MHz" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockXT24MHz">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockXT24MHz">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockXT24MHz">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockXT24MHz">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
</dependencies>
<clock_sources/>
<clock_outputs>
<clock_output id="AHB_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CAN_CLK_ROOT.outFreq" value="2 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="LCDIF_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="LVDS1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="PLL7_MAIN_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK1.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK3.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="1.5 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="4 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.ARM_PODF.scale" value="1" locked="false"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="1" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="1" locked="false"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
<setting id="CCM_ANALOG_PLL_ARM_POWERDOWN_CFG" value="Yes" locked="false"/>
<setting id="CCM_ANALOG_PLL_SYS_POWERDOWN_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>false</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
@ -269,7 +380,7 @@
<file path="board/dcd.h" update_enabled="true"/>
</generated_project_files>
<dcdx_profile>
<processor_version>11.0.1</processor_version>
<processor_version>12.0.0</processor_version>
<output_format>c_array</output_format>
</dcdx_profile>
<dcdx_configurations>
@ -286,7 +397,7 @@
<file path="board/peripherals.h" update_enabled="true"/>
</generated_project_files>
<peripherals_profile>
<processor_version>11.0.1</processor_version>
<processor_version>12.0.0</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="19596643-a9d0-4000-b44d-6a0a05ec6830" called_from_default_init="true" id_prefix="" core="core0">

200
board/board.c
View File

@ -8,9 +8,6 @@
#include "fsl_common.h"
#include "fsl_debug_console.h"
#include "board.h"
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
#include "fsl_lpi2c.h"
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#include "fsl_iomuxc.h"
/*******************************************************************************
* Variables
@ -47,203 +44,6 @@ void BOARD_InitDebugConsole(void)
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
}
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
{
lpi2c_master_config_t lpi2cConfig = {0};
/*
* lpi2cConfig.debugEnable = false;
* lpi2cConfig.ignoreAck = false;
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
* lpi2cConfig.baudRate_Hz = 100000U;
* lpi2cConfig.busIdleTimeout_ns = 0;
* lpi2cConfig.pinLowTimeout_ns = 0;
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
*/
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
}
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Write;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = txBuff;
xfer.dataSize = txBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Read;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = rxBuff;
xfer.dataSize = rxBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Write;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = txBuff;
xfer.dataSize = txBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
status_t status;
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Write;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = NULL;
xfer.dataSize = 0;
status = LPI2C_MasterTransferBlocking(base, &xfer);
if (kStatus_Success == status)
{
xfer.subaddressSize = 0;
xfer.direction = kLPI2C_Read;
xfer.data = rxBuff;
xfer.dataSize = rxBuffSize;
status = LPI2C_MasterTransferBlocking(base, &xfer);
}
return status;
}
void BOARD_Accel_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
}
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
{
uint8_t data = (uint8_t)txBuff;
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
}
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
}
void BOARD_Codec_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
}
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
}
void BOARD_Camera_I2C_Init(void)
{
CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
}
status_t BOARD_Camera_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Camera_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
rxBuffSize);
}
status_t BOARD_Camera_I2C_SendSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Camera_I2C_ReceiveSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
rxBuffSize);
}
status_t BOARD_Touch_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Touch_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
}
#endif /* SDK_I2C_BASED_COMPONENT_USED */
/* MPU configuration. */
void BOARD_ConfigMPU(void)
{

83
board/board.h
View File

@ -17,7 +17,7 @@
* Definitions
******************************************************************************/
/*! @brief The board name */
#define BOARD_NAME "IMXRT1050-EVKB"
#define BOARD_NAME "LQ-RT1052SYS-VA1"
/* The UART to use for debug messages. */
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
@ -75,26 +75,8 @@
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
#define BOARD_ARDUINO_I2C_INDEX (1)
#define BOARD_HAS_SDCARD (1U)
/* @Brief Board accelerator sensor configuration */
#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
/* Clock divider for LPI2C clock source */
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
#define BOARD_CODEC_I2C_INSTANCE 1U
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
/* @Brief Board CAMERA configuration */
#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
@ -109,19 +91,6 @@
#define BOARD_CAMERA_PWDN_GPIO GPIO1
#define BOARD_CAMERA_PWDN_PIN 4
/* @Brief Board touch panel configuration */
#define BOARD_TOUCH_I2C_BASEADDR LPI2C1
#define BOARD_TOUCH_RST_GPIO GPIO1
#define BOARD_TOUCH_RST_PIN 2
#define BOARD_TOUCH_INT_GPIO GPIO1
#define BOARD_TOUCH_INT_PIN 11
/* @Brief Board Bluetooth HCI UART configuration */
#define BOARD_BT_UART_BASEADDR LPUART3
#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
#define BOARD_BT_UART_IRQ LPUART3_IRQn
#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
@ -134,56 +103,6 @@ uint32_t BOARD_DebugConsoleSrcFreq(void);
void BOARD_InitDebugConsole(void);
void BOARD_ConfigMPU(void);
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
void BOARD_Accel_I2C_Init(void);
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Codec_I2C_Init(void);
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Camera_I2C_Init(void);
status_t BOARD_Camera_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Camera_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
status_t BOARD_Camera_I2C_SendSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Camera_I2C_ReceiveSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
status_t BOARD_Touch_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Touch_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#if defined(__cplusplus)
}

1181
board/clock_config.c
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File diff suppressed because it is too large Load Diff

305
board/clock_config.h
View File

@ -28,73 +28,73 @@ void BOARD_InitBootClocks(void);
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************* Configuration Board_BootClockPLL600MHz ********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
* Definitions for Board_BootClockPLL600MHz configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
#define BOARD_BOOTCLOCKPLL600MHZ_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 2000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 0UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 2000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 3000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 3000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 6000000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 3000000UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 3000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 3000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 1500000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 3000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 1500000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 3000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 1500000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 6000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CAN_CLK_ROOT 2000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CKIL_SYNC_CLK_ROOT 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO1_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXIO2_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_GPT1_IPG_CLK_HIGHFREQ5000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_GPT2_IPG_CLK_HIGHFREQ5000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LCDIF_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LPI2C_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKPLL600MHZ_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_MQS_MCLK 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_PERCLK_CLK_ROOT 5000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK1 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK2 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI1_MCLK3 1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK1 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI2_MCLK3 1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK1 3000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_SAI3_MCLK3 1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SEMC_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKPLL600MHZ_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_TRACE_CLK_ROOT 88000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_UART_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKPLL600MHZ_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKPLL600MHZ_USDHC2_CLK_ROOT 198000000UL
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
/*! @brief Arm PLL set for Board_BootClockPLL600MHz configuration.
*/
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL600MHz;
/*! @brief Sys PLL for Board_BootClockPLL600MHz configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL600MHz;
/*! @brief Enet PLL set for Board_BootClockPLL600MHz configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL600MHz;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
* API for Board_BootClockPLL600MHz configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
@ -104,80 +104,80 @@ extern "C" {
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
void Board_BootClockPLL600MHz(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration Board_BootClock600MHz **********************
******************* Configuration Board_BootClockPLL480MHz ********************
******************************************************************************/
/*******************************************************************************
* Definitions for Board_BootClock600MHz configuration
* Definitions for Board_BootClockPLL480MHz configuration
******************************************************************************/
#define BOARD_BOOTCLOCK600MHZ_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */
#define BOARD_BOOTCLOCKPLL480MHZ_CORE_CLOCK 480000000U /*!< Core clock frequency: 480000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCK600MHZ_AHB_CLK_ROOT 528000000UL
#define BOARD_BOOTCLOCK600MHZ_CAN_CLK_ROOT 2000000UL
#define BOARD_BOOTCLOCK600MHZ_CKIL_SYNC_CLK_ROOT 0UL
#define BOARD_BOOTCLOCK600MHZ_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCK600MHZ_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCK600MHZ_CLK_1M 1000000UL
#define BOARD_BOOTCLOCK600MHZ_CLK_24M 24000000UL
#define BOARD_BOOTCLOCK600MHZ_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCK600MHZ_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCK600MHZ_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCK600MHZ_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCK600MHZ_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCK600MHZ_FLEXIO1_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCK600MHZ_FLEXIO2_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCK600MHZ_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCK600MHZ_GPT1_IPG_CLK_HIGHFREQ 4000000UL
#define BOARD_BOOTCLOCK600MHZ_GPT2_IPG_CLK_HIGHFREQ 4000000UL
#define BOARD_BOOTCLOCK600MHZ_IPG_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCK600MHZ_LCDIF_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCK600MHZ_LPI2C_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCK600MHZ_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCK600MHZ_LVDS1_CLK 1056000000UL
#define BOARD_BOOTCLOCK600MHZ_MQS_MCLK 3000000UL
#define BOARD_BOOTCLOCK600MHZ_PERCLK_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCK600MHZ_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI1_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI1_MCLK1 3000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI1_MCLK2 3000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI1_MCLK3 1500000UL
#define BOARD_BOOTCLOCK600MHZ_SAI2_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI2_MCLK1 3000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCK600MHZ_SAI2_MCLK3 1500000UL
#define BOARD_BOOTCLOCK600MHZ_SAI3_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI3_MCLK1 3000000UL
#define BOARD_BOOTCLOCK600MHZ_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCK600MHZ_SAI3_MCLK3 1500000UL
#define BOARD_BOOTCLOCK600MHZ_SEMC_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCK600MHZ_SPDIF0_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCK600MHZ_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCK600MHZ_TRACE_CLK_ROOT 88000000UL
#define BOARD_BOOTCLOCK600MHZ_UART_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCK600MHZ_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCK600MHZ_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCK600MHZ_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCK600MHZ_USDHC2_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_AHB_CLK_ROOT 480000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CAN_CLK_ROOT 2000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CKIL_SYNC_CLK_ROOT 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO1_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXIO2_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_GPT1_IPG_CLK_HIGHFREQ4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_GPT2_IPG_CLK_HIGHFREQ4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_IPG_CLK_ROOT 120000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LCDIF_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LPI2C_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKPLL480MHZ_LVDS1_CLK 960000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_MQS_MCLK 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_PERCLK_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK1 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK2 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI1_MCLK3 1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK1 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI2_MCLK3 1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK1 3000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_SAI3_MCLK3 1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SEMC_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKPLL480MHZ_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_TRACE_CLK_ROOT 88000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_UART_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKPLL480MHZ_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKPLL480MHZ_USDHC2_CLK_ROOT 198000000UL
/*! @brief Arm PLL set for Board_BootClock600MHz configuration.
/*! @brief Arm PLL set for Board_BootClockPLL480MHz configuration.
*/
extern const clock_arm_pll_config_t armPllConfig_Board_BootClock600MHz;
/*! @brief Sys PLL for Board_BootClock600MHz configuration.
extern const clock_arm_pll_config_t armPllConfig_Board_BootClockPLL480MHz;
/*! @brief Sys PLL for Board_BootClockPLL480MHz configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_Board_BootClock600MHz;
/*! @brief Enet PLL set for Board_BootClock600MHz configuration.
extern const clock_sys_pll_config_t sysPllConfig_Board_BootClockPLL480MHz;
/*! @brief Enet PLL set for Board_BootClockPLL480MHz configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_Board_BootClock600MHz;
extern const clock_enet_pll_config_t enetPllConfig_Board_BootClockPLL480MHz;
/*******************************************************************************
* API for Board_BootClock600MHz configuration
* API for Board_BootClockPLL480MHz configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
@ -187,7 +187,84 @@ extern "C" {
* @brief This function executes configuration of clocks.
*
*/
void Board_BootClock600MHz(void);
void Board_BootClockPLL480MHz(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockXT24MHz *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockXT24MHz configuration
******************************************************************************/
#define BOARD_BOOTCLOCKXT24MHZ_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKXT24MHZ_AHB_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CAN_CLK_ROOT 2000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CKIL_SYNC_CLK_ROOT 0UL
#define BOARD_BOOTCLOCKXT24MHZ_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKXT24MHZ_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKXT24MHZ_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKXT24MHZ_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO1_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_FLEXIO2_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_FLEXSPI_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_GPT1_IPG_CLK_HIGHFREQ 6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_GPT2_IPG_CLK_HIGHFREQ 6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_IPG_CLK_ROOT 6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LCDIF_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LPI2C_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LPSPI_CLK_ROOT 6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_LVDS1_CLK 24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_MQS_MCLK 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_PERCLK_CLK_ROOT 6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK1 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK2 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI1_MCLK3 1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK1 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI2_MCLK3 1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_CLK_ROOT 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK1 3000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKXT24MHZ_SAI3_MCLK3 1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SEMC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_CLK_ROOT 1500000UL
#define BOARD_BOOTCLOCKXT24MHZ_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKXT24MHZ_TRACE_CLK_ROOT 6000000UL
#define BOARD_BOOTCLOCKXT24MHZ_UART_CLK_ROOT 4000000UL
#define BOARD_BOOTCLOCKXT24MHZ_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKXT24MHZ_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKXT24MHZ_USDHC1_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKXT24MHZ_USDHC2_CLK_ROOT 12000000UL
/*! @brief Enet PLL set for BOARD_BootClockXT24MHz configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockXT24MHz;
/*******************************************************************************
* API for BOARD_BootClockXT24MHz configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockXT24MHz(void);
#if defined(__cplusplus)
}

2
board/dcd.c
View File

@ -24,7 +24,7 @@ product: DCDx v3.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 11.0.1
processor_version: 12.0.0
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */

2
board/peripherals.c
View File

@ -10,7 +10,7 @@ product: Peripherals v11.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 11.0.1
processor_version: 12.0.0
functionalGroups:
- name: BOARD_InitPeripherals
UUID: 19596643-a9d0-4000-b44d-6a0a05ec6830

53
board/pin_mux.c
View File

@ -6,11 +6,11 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v11.0
product: Pins v12.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 11.0.1
processor_version: 12.0.0
pin_labels:
- {pin_num: C7, pin_signal: GPIO_EMC_41, label: LED_B, identifier: LED_R;LED_B}
- {pin_num: B12, pin_signal: GPIO_B1_07, label: LED_G, identifier: LED_G}
@ -30,16 +30,47 @@ pin_labels:
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDbgConsolePins();
BOARD_InitLEDPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
BOARD_InitDbgConsolePins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDbgConsolePins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDbgConsolePins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
#endif
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitLEDPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: C7, peripheral: GPIO3, signal: 'gpio_io, 27', pin_signal: GPIO_EMC_41, identifier: LED_B, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: B12, peripheral: GPIO2, signal: 'gpio_io, 23', pin_signal: GPIO_B1_07, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: A7, peripheral: GPIO3, signal: 'gpio_io, 26', pin_signal: GPIO_EMC_40, identifier: LED_R, direction: OUTPUT, gpio_init_state: 'true'}
@ -48,11 +79,11 @@ BOARD_InitPins:
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Function Name : BOARD_InitLEDPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
void BOARD_InitLEDPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of LED_G on GPIO_B1_07 (pin B12) */
@ -82,16 +113,6 @@ void BOARD_InitPins(void) {
/* Initialize GPIO functionality on GPIO_EMC_41 (pin C7) */
GPIO_PinInit(GPIO3, 27U, &LED_B_config);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
#endif
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_GPIO2_IO23, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_GPIO3_IO26, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_GPIO3_IO27, 0U);

63
board/pin_mux.h
View File

@ -37,54 +37,61 @@ extern "C" {
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDbgConsolePins(void);
/* GPIO_EMC_41 (coord C7), LED_B */
/* Routed pin properties */
#define BOARD_INITPINS_LED_B_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITPINS_LED_B_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LED_B_CHANNEL 27U /*!< Signal channel */
#define BOARD_INITLEDPINS_LED_B_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITLEDPINS_LED_B_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITLEDPINS_LED_B_CHANNEL 27U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LED_B_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LED_B_GPIO_PIN 27U /*!< GPIO pin number */
#define BOARD_INITPINS_LED_B_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LED_B_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LED_B_PIN 27U /*!< PORT pin number */
#define BOARD_INITPINS_LED_B_PIN_MASK (1U << 27U) /*!< PORT pin mask */
#define BOARD_INITLEDPINS_LED_B_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITLEDPINS_LED_B_GPIO_PIN 27U /*!< GPIO pin number */
#define BOARD_INITLEDPINS_LED_B_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */
#define BOARD_INITLEDPINS_LED_B_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITLEDPINS_LED_B_PIN 27U /*!< PORT pin number */
#define BOARD_INITLEDPINS_LED_B_PIN_MASK (1U << 27U) /*!< PORT pin mask */
/* GPIO_B1_07 (coord B12), LED_G */
/* Routed pin properties */
#define BOARD_INITPINS_LED_G_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITPINS_LED_G_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LED_G_CHANNEL 23U /*!< Signal channel */
#define BOARD_INITLEDPINS_LED_G_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITLEDPINS_LED_G_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITLEDPINS_LED_G_CHANNEL 23U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LED_G_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LED_G_GPIO_PIN 23U /*!< GPIO pin number */
#define BOARD_INITPINS_LED_G_GPIO_PIN_MASK (1U << 23U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LED_G_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LED_G_PIN 23U /*!< PORT pin number */
#define BOARD_INITPINS_LED_G_PIN_MASK (1U << 23U) /*!< PORT pin mask */
#define BOARD_INITLEDPINS_LED_G_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITLEDPINS_LED_G_GPIO_PIN 23U /*!< GPIO pin number */
#define BOARD_INITLEDPINS_LED_G_GPIO_PIN_MASK (1U << 23U) /*!< GPIO pin mask */
#define BOARD_INITLEDPINS_LED_G_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITLEDPINS_LED_G_PIN 23U /*!< PORT pin number */
#define BOARD_INITLEDPINS_LED_G_PIN_MASK (1U << 23U) /*!< PORT pin mask */
/* GPIO_EMC_40 (coord A7), LED_R */
/* Routed pin properties */
#define BOARD_INITPINS_LED_R_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITPINS_LED_R_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LED_R_CHANNEL 26U /*!< Signal channel */
#define BOARD_INITLEDPINS_LED_R_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITLEDPINS_LED_R_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITLEDPINS_LED_R_CHANNEL 26U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LED_R_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LED_R_GPIO_PIN 26U /*!< GPIO pin number */
#define BOARD_INITPINS_LED_R_GPIO_PIN_MASK (1U << 26U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LED_R_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LED_R_PIN 26U /*!< PORT pin number */
#define BOARD_INITPINS_LED_R_PIN_MASK (1U << 26U) /*!< PORT pin mask */
#define BOARD_INITLEDPINS_LED_R_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITLEDPINS_LED_R_GPIO_PIN 26U /*!< GPIO pin number */
#define BOARD_INITLEDPINS_LED_R_GPIO_PIN_MASK (1U << 26U) /*!< GPIO pin mask */
#define BOARD_INITLEDPINS_LED_R_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITLEDPINS_LED_R_PIN 26U /*!< PORT pin number */
#define BOARD_INITLEDPINS_LED_R_PIN_MASK (1U << 26U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
void BOARD_InitLEDPins(void);
#if defined(__cplusplus)
}

6
src/main.c
View File

@ -15,9 +15,9 @@ int main(void) {
CLOCK_SetMode(kCLOCK_ModeRun);
GPIO_WritePinOutput(BOARD_INITPINS_LED_R_GPIO, BOARD_INITPINS_LED_R_PIN, 0U);
GPIO_WritePinOutput(BOARD_INITPINS_LED_G_GPIO, BOARD_INITPINS_LED_G_PIN, 0U);
GPIO_WritePinOutput(BOARD_INITPINS_LED_B_GPIO, BOARD_INITPINS_LED_B_PIN, 0U);
GPIO_WritePinOutput(BOARD_INITLEDPINS_LED_R_GPIO, BOARD_INITLEDPINS_LED_R_PIN, 0U);
GPIO_WritePinOutput(BOARD_INITLEDPINS_LED_G_GPIO, BOARD_INITLEDPINS_LED_G_PIN, 0U);
GPIO_WritePinOutput(BOARD_INITLEDPINS_LED_B_GPIO, BOARD_INITLEDPINS_LED_B_PIN, 0U);
for (;;) {
__WFI();