generated from Embedded_Projects/MPyATE_Template
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
/* Board */
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#include "clock_config.h"
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#include "pin_mux.h"
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/* SDK drivers */
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#include "fsl_clock.h"
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#include "fsl_dac.h"
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#include "fsl_power.h"
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/* Private */
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#include "app_dac.h"
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#define APP_DAC_REG_OFFSET_CTRL (0x00U)
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#define APP_DAC_REG_OFFSET_DATA (0x01U)
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#define APP_DAC_CTRL_BIAS_Pos (8U)
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#define APP_DAC_CTRL_BIAS_Msk (1U << APP_DAC_CTRL_BIAS_Pos)
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static inline uint16_t app_dac_read_reg_ctrl(void);
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static inline uint16_t app_dac_read_reg_data(void);
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static inline void app_dac_write_reg_ctrl(uint16_t data);
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static inline void app_dac_write_reg_data(uint16_t data);
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void app_dac_init(void) {
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POWER_DisablePD(kPDRUNCFG_PD_DAC0);
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CLOCK_EnableClock(kCLOCK_Dac);
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RESET_PeripheralReset(kDAC0_RST_N_SHIFT_RSTn);
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DAC0->CR = 0UL;
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DAC0->CTRL = 0UL;
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}
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uint16_t app_dac_module_reg_read(uint8_t addr) {
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uint16_t ret = 0x5555;
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switch (addr) {
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case APP_DAC_REG_OFFSET_CTRL:
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ret = app_dac_read_reg_ctrl();
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break;
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case APP_DAC_REG_OFFSET_DATA:
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ret = app_dac_read_reg_data();
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break;
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default:
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break;
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}
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return ret;
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}
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void app_dac_module_reg_write(uint8_t addr, uint16_t data) {
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switch (addr) {
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case APP_DAC_REG_OFFSET_CTRL:
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app_dac_write_reg_ctrl(data);
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break;
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case APP_DAC_REG_OFFSET_DATA:
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app_dac_write_reg_data(data);
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break;
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default:
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break;
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}
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}
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static inline uint16_t app_dac_read_reg_ctrl(void) {
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uint16_t ret = 0x0000U;
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if (DAC0->CR & DAC_CR_BIAS_MASK) {
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ret |= APP_DAC_CTRL_BIAS_Msk;
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}
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return ret;
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}
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static inline uint16_t app_dac_read_reg_data(void) {
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return ((DAC0->CR & DAC_CR_VALUE_MASK) >> DAC_CR_VALUE_SHIFT);
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}
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static inline void app_dac_write_reg_ctrl(uint16_t data) {
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if (data & APP_DAC_CTRL_BIAS_Msk) {
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DAC0->CR |= DAC_CR_BIAS_MASK;
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} else {
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DAC0->CR &= ~DAC_CR_BIAS_MASK;
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}
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}
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static inline void app_dac_write_reg_data(uint16_t data) {
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uint32_t cr = DAC0->CR;
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cr &= ~DAC_CR_VALUE_MASK;
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cr |= DAC_CR_VALUE(data);
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DAC0->CR = cr;
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} |