Fixed SysTick clock source and debug server script.
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0e6f106c87
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013cd0a5c5
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@ -14,7 +14,7 @@ run_openocd_jlink() {
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run_pyocd() {
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run_pyocd() {
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echo "Note: pyOCD uses low level DAP APIs provided by J-LINK," \
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echo "Note: pyOCD uses low level DAP APIs provided by J-LINK," \
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"speed settings and other functions may not available."
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"speed settings and other functions may not available."
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pyocd gdbserver -t stm32h750vbtx -f 4m --persist
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pyocd gdbserver -t nuc220le3an -f 4m --persist
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}
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}
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case $1 in
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case $1 in
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@ -58,9 +58,13 @@ static void system_clock_config(void) {
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* Clear the latch manually after clock changes.
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* Clear the latch manually after clock changes.
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*/
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*/
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SYS_UnlockReg();
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SYS_UnlockReg();
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CLK->CLKSEL0 = CLK_CLKSEL0_STCLK_S_HCLK | CLK_CLKSEL0_HCLK_S_PLL; /* SysTick and HCLK */
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CLK->CLKSEL0 = CLK_CLKSEL0_HCLK_S_PLL; /* HCLK */
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SYS_LockReg();
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SYS_LockReg();
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SysTick->CTRL &= ~(SysTick_CTRL_CLKSOURCE_Msk); /* SysTick */
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SysTick->CTRL |= CLK_CLKSEL0_STCLK_S_HCLK;
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CLK->CLKSEL1 = 0xFFFFFFFF; /* Reset value */
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CLK->CLKSEL1 = 0xFFFFFFFF; /* Reset value */
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CLK->CLKSEL1 &= ~CLK_CLKSEL1_SPI0_S_Msk;
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CLK->CLKSEL1 &= ~CLK_CLKSEL1_SPI0_S_Msk;
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CLK->CLKSEL1 |= CLK_CLKSEL1_SPI0_S_HCLK;
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CLK->CLKSEL1 |= CLK_CLKSEL1_SPI0_S_HCLK;
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