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Update IRQ handlers.

This commit is contained in:
imi415 2022-08-08 09:12:06 +08:00
parent 57b43c4816
commit c6c633655d
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
4 changed files with 138 additions and 65 deletions
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136
include/stx7105.h
View File

@ -8,41 +8,41 @@
typedef struct {
__IO uint8_t POUT; /* Offset: 0x00, GPIO pin output register */
__IO uint8_t UNUSED0[3]; /* Offset: 0x01 */
uint8_t UNUSED0[3]; /* Offset: 0x01 */
__IO uint8_t SET_POUT; /* Offset: 0x04, GPIO pin output set register */
__IO uint8_t UNUSED1[3]; /* Offset: 0x05 */
uint8_t UNUSED1[3]; /* Offset: 0x05 */
__IO uint8_t CLR_POUT; /* Offset: 0x08, GPIO pin output clear register */
__IO uint8_t UNUSED2[7]; /* Offset: 0x09 */
uint8_t UNUSED2[7]; /* Offset: 0x09 */
__IO uint8_t PIN; /* Offset: 0x10, GPIO pin input register */
__IO uint8_t UNUSED3[15]; /* Offset: 0x11 */
uint8_t UNUSED3[15]; /* Offset: 0x11 */
__IO uint8_t PC0; /* Offset: 0x20, GPIO pin config register 0 */
__IO uint8_t UNUSED4[3]; /* Offset: 0x21 */
uint8_t UNUSED4[3]; /* Offset: 0x21 */
__IO uint8_t SET_PC0; /* Offset: 0x24, GPIO pin config set register 0 */
__IO uint8_t UNUSED5[3]; /* Offset: 0x25 */
uint8_t UNUSED5[3]; /* Offset: 0x25 */
__IO uint8_t CLR_PC0; /* Offset: 0x28, GPIO pin config clear register 0 */
__IO uint8_t UNUSED6[7]; /* Offset: 0x29 */
uint8_t UNUSED6[7]; /* Offset: 0x29 */
__IO uint8_t PC1; /* Offset: 0x30, GPIO pin config register 1 */
__IO uint8_t UNUSED7[3]; /* Offset: 0x31 */
uint8_t UNUSED7[3]; /* Offset: 0x31 */
__IO uint8_t SET_PC1; /* Offset: 0x34, GPIO pin config set register 1 */
__IO uint8_t UNUSED8[3]; /* Offset: 0x35 */
uint8_t UNUSED8[3]; /* Offset: 0x35 */
__IO uint8_t CLR_PC1; /* Offset: 0x38, GPIO pin config clear register 1 */
__IO uint8_t UNUSED9[7]; /* Offset: 0x39 */
uint8_t UNUSED9[7]; /* Offset: 0x39 */
__IO uint8_t PC2; /* Offset: 0x40, GPIO pin config register 2 */
__IO uint8_t UNUSED10[3]; /* Offset: 0x41 */
uint8_t UNUSED10[3]; /* Offset: 0x41 */
__IO uint8_t SET_PC2; /* Offset: 0x44, GPIO pin config set register 2 */
__IO uint8_t UNUSED11[3]; /* Offset: 0x45 */
uint8_t UNUSED11[3]; /* Offset: 0x45 */
__IO uint8_t CLR_PC2; /* Offset: 0x48, GPIO pin config clear register 2 */
__IO uint8_t UNUSED12[7]; /* Offset: 0x49 */
uint8_t UNUSED12[7]; /* Offset: 0x49 */
__IO uint8_t PCOMP; /* Offset: 0x50, GPIO pin input comparison register */
__IO uint8_t UNUSED13[3]; /* Offset: 0x51 */
uint8_t UNUSED13[3]; /* Offset: 0x51 */
__IO uint8_t SET_PCOMP; /* Offset: 0x54, GPIO pin input comparison set regiser */
__IO uint8_t UNUSED14[3]; /* Offset: 0x55 */
uint8_t UNUSED14[3]; /* Offset: 0x55 */
__IO uint8_t CLR_PCOMP; /* Offset: 0x58, GPIO pin input comparison clear regiser */
__IO uint8_t UNUSED15[7]; /* Offset: 0x59 */
uint8_t UNUSED15[7]; /* Offset: 0x59 */
__IO uint8_t PMASK; /* Offset: 0x60, GPIO pin input comparison mask register */
__IO uint8_t UNUSED16[3]; /* Offset: 0x61 */
uint8_t UNUSED16[3]; /* Offset: 0x61 */
__IO uint8_t SET_PMASK; /* Offset: 0x64, GPIO pin input comparison mask set regiser */
__IO uint8_t UNUSED17[3]; /* Offset: 0x65 */
uint8_t UNUSED17[3]; /* Offset: 0x65 */
__IO uint8_t CLR_PMASK; /* Offset: 0x68, GPIO pin input comparison mask clear regiser */
} PIO_TypeDef;
@ -60,6 +60,19 @@ typedef struct {
__IO uint32_t RETRIES; /* Offset: 0x28, ASCn number of retries on transmission register */
} ASC_TypeDef;
typedef struct {
__IO uint16_t ICR; /* Offset: 0x00, Interrupt control register */
uint8_t UNUSED0[2]; /* Offset: 0x02 */
__IO uint16_t IPRA; /* Offset: 0x04, Interrupt priority level A register */
uint8_t UNUSED1[2]; /* Offset: 0x06 */
__IO uint16_t IPRB; /* Offset: 0x08, Interrupt priority level B register */
uint8_t UNUSED2[2]; /* Offset: 0x0A */
__IO uint16_t IPRC; /* Offset: 0x0C, Interrupt priority level C register */
uint8_t UNUSED3[2]; /* Offset: 0x0E */
__IO uint16_t IPRD; /* Offset: 0x10, Interrupt priority level D register */
uint8_t UNUSED4[2]; /* Offset: 0x12 */
} INTC_TypeDef;
typedef struct {
__IO uint8_t TOCR; /* Offset: 0x00, Timer output control register */
uint8_t UNUSED0[3]; /* Offset: 0x01 */
@ -81,46 +94,89 @@ typedef struct {
} TMU_TypeDef;
typedef struct {
__IO uint32_t PTEH; /* Offset: 0x00, Page table entry high register */
__IO uint32_t PTEL; /* Offset: 0x04, Page table entry low register */
__IO uint32_t TTB; /* Offset: 0x08, Translation table base register */
__IO uint32_t TEA; /* Offset: 0x0C, TLB exception address register */
__IO uint32_t MMUCR; /* Offset: 0x10, MMU control register */
__IO uint8_t BASRA; /* Offset: 0x14, Break ASID register A*/
uint8_t UNUSED0[3]; /* Offset: 0x15 */
__IO uint8_t BASRB; /* Offset: 0x18, Break ASID register B*/
uint8_t UNUSED1[3]; /* Offset: 0x19 */
__IO uint32_t CCR; /* Offset: 0x1C, Cache control register */
__IO uint32_t TRA; /* Offset: 0x20, TRAPA exception register */
__IO uint32_t EXPEVT; /* Offset: 0x24, Exception event register */
__IO uint32_t INTEVT; /* Offset: 0x28, Interrupt event register */
uint32_t UNUSED2[3]; /* Offset: 0x2C */
__IO uint32_t QACR0; /* Offset: 0x38, Queue address control register 0 */
__IO uint32_t QACR1; /* Offset: 0x3C, Queue address control register 1 */
uint32_t UNUSED3[12]; /* Offset: 0x40 */
__IO uint32_t PASCR; /* Offset: 0x70, Physical address space control register */
__IO uint32_t RAMCR; /* Offset: 0x74, On-chip memory control register */
__IO uint32_t IRMCR; /* Offset: 0x78, Instruction refetch inhibit control register */
__IO uint32_t PTEH; /* Offset: 0x00000, Page table entry high register */
__IO uint32_t PTEL; /* Offset: 0x00004, Page table entry low register */
__IO uint32_t TTB; /* Offset: 0x00008, Translation table base register */
__IO uint32_t TEA; /* Offset: 0x0000C, TLB exception address register */
__IO uint32_t MMUCR; /* Offset: 0x00010, MMU control register */
__IO uint8_t BASRA; /* Offset: 0x00014, Break ASID register A*/
uint8_t UNUSED0[3]; /* Offset: 0x00015 */
__IO uint8_t BASRB; /* Offset: 0x00018, Break ASID register B*/
uint8_t UNUSED1[3]; /* Offset: 0x00019 */
__IO uint32_t CCR; /* Offset: 0x0001C, Cache control register */
__IO uint32_t TRA; /* Offset: 0x00020, TRAPA exception register */
__IO uint32_t EXPEVT; /* Offset: 0x00024, Exception event register */
__IO uint32_t INTEVT; /* Offset: 0x00028, Interrupt event register */
uint32_t UNUSED2[3]; /* Offset: 0x0002C */
__IO uint32_t QACR0; /* Offset: 0x00038, Queue address control register 0 */
__IO uint32_t QACR1; /* Offset: 0x0003C, Queue address control register 1 */
uint32_t UNUSED3[12]; /* Offset: 0x00040 */
__IO uint32_t PASCR; /* Offset: 0x00070, Physical address space control register */
__IO uint32_t RAMCR; /* Offset: 0x00074, On-chip memory control register */
__IO uint32_t IRMCR; /* Offset: 0x00078, Instruction refetch inhibit control register */
uint32_t UNUSED4[2097028]; /* Offset: 0x0007C, Am I serious? */
__IO uint32_t BARA; /* Offset: 0x20000, Break address register A */
__IO uint8_t BAMRA; /* Offset: 0x20004, Break address mask register A */
uint8_t UNUSED5[3]; /* Offset: 0x20005 */
__IO uint16_t BBRA; /* Offset: 0x20008, Break bus cycle register A */
uint8_t UNUSED6[2]; /* Offset: 0x2000A */
__IO uint32_t BARB; /* Offset: 0x2000B, Break address register B */
__IO uint8_t BAMRB; /* Offset: 0x20010, Break address mask register B */
uint8_t UNUSED7[3]; /* Offset: 0x20011 */
__IO uint16_t BBRB; /* Offset: 0x20014, Break bus cycle register B */
uint8_t UNUSED8[2]; /* Offset: 0x20016 */
__IO uint32_t BDRB; /* Offset: 0x20018, Break data register B */
__IO uint32_t BDMRB; /* Offset: 0x2001C, Break data mask register B */
__IO uint16_t BRCR; /* Offset: 0x20020, Break control register */
uint8_t UNUSED9[2]; /* Offset: 0x20022 */
} CSR_TypeDef;
#define XX sizeof(TMU_TypeDef)
#define PIO0_BASE (0xFD020000U)
#define PIO1_BASE (0xFD021000U)
#define PIO2_BASE (0xFD022000U)
#define PIO3_BASE (0xFD023000U)
#define PIO4_BASE (0xFD024000U)
#define PIO5_BASE (0xFD025000U)
#define PIO6_BASE (0xFD026000U)
#define ASC0_BASE (0xFD030000U)
#define ASC1_BASE (0xFD031000U)
#define ASC2_BASE (0xFD032000U)
#define ASC3_BASE (0xFD033000U)
#define CSR_BASE (0xFF000000U)
#define INTC_BASE (0xFFD00000U)
#define TMU_BASE (0xFFD80000U)
#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
#define PIO1 ((PIO_TypeDef *)PIO1_BASE)
#define PIO2 ((PIO_TypeDef *)PIO2_BASE)
#define PIO3 ((PIO_TypeDef *)PIO3_BASE)
#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
#define PIO5 ((PIO_TypeDef *)PIO5_BASE)
#define PIO6 ((PIO_TypeDef *)PIO6_BASE)
#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
#define CSR ((CSR_TypeDef *)CSR_BASE)
#define INTC ((INTC_TypeDef *)INTC_BASE)
#define TMU ((TMU_TypeDef *)TMU_BASE)
#define TMU_TSTR_STR0_Pos 0
#define TMU_TSTR_STR0_Msk (1U << TMU_TSTR_STR0_Pos)
#define TMU_TSTR_STR1_Pos 1
#define TMU_TSTR_STR1_Msk (1U << TMU_TSTR_STR1_Pos)
#define TMU_TSTR_STR2_Pos 2
#define TMU_TSTR_STR3_Msk (1U << TMU_TSTR_STR2_Pos)
#define TMU_TCR_UNIE_Pos 5
#define TMU_TCR_UNIE_Msk (1U << TMU_TCR_UNIE_Pos)
#define TMU_TCR_UNF_Pos 8
#define TMU_TCR_UNF_Msk (1U << TMU_TCR_UNF_Pos)
#define INTC_IPRA_IPR_TMU0_Pos 12
#define INTC_IPRA_IPR_TMU0_Msk (0x0FU << INTC_IPRA_IPR_TMU0_Pos)
#endif

30
src/stx7105_exc.c
View File

@ -9,29 +9,23 @@ typedef enum {
} expevt_type_t;
typedef enum {
INT_TYPE_TMU = 0x000,
INT_TYPE_TMU_TNUI0 = 0x400,
INT_TYPE_TMU_TNUI1 = 0x420,
INT_TYPE_TMU_TNUI2 = 0x440,
INT_TYPE_TMU_TICPI2 = 0x460,
} intevt_type_t;
typedef enum {
TRA_TYPE_SYSCALL = 34,
} tra_type_t;
static int uart_write(char *ptr, int len) {
for (int i = 0; i < len; i++) {
while (ASC2->STA & 0x200) {
/* TX FIFO full... */
}
ASC2->TX_BUF = (uint8_t)ptr[i];
}
return len;
__WEAK int tuni0_handler(void) {
/* Does nothing */
return 0;
}
__WEAK int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
if (p1 == 4) {
return uart_write((char *)p3, (int)p4);
}
return 0;
}
@ -53,7 +47,7 @@ __WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32
expevt_type_t expevt = CSR->EXPEVT;
switch (expevt) {
case EXP_TYPE_TRAP:
trap_handler(p1, p2, p3, p4);
return trap_handler(p1, p2, p3, p4);
break;
default:
break;
@ -63,5 +57,13 @@ __WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32
}
__WEAK_IRQ int general_int_handler(void) {
intevt_type_t intevt = CSR->INTEVT;
switch (intevt) {
case INT_TYPE_TMU_TNUI0:
return tuni0_handler();
break;
default:
break;
}
return 0;
}

35
src/stx7105_utils.c
View File

@ -1,6 +1,10 @@
#include "stx7105.h"
/* Private */
#include "stx7105_utils.h"
volatile uint8_t s_tmu_flag = 0U;
void init_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t init_value) {
gpiox->CLR_PC0 = 1 << pin;
gpiox->SET_PC1 = 1 << pin;
@ -25,17 +29,28 @@ void delay_ms(uint32_t msec) {
uint32_t reload_value = msec * 66 - 1;
TMU->TSTR &= ~1U; /* Stop counter */
TMU->TCR0 = 0x04U; /* 1024 prescale */
TMU->TCNT0 = reload_value; /* 66kHz */
TMU->TCOR0 = reload_value; /* Reload register */
TMU->TSTR |= 1U; /* Start counter */
TMU->TSTR &= ~TMU_TSTR_STR0_Msk; /* Stop counter */
TMU->TCR0 = 0x04U | TMU_TCR_UNIE_Msk; /* 1024 prescale, enable interrupt */
TMU->TCNT0 = reload_value; /* 66kHz */
TMU->TCOR0 = reload_value; /* Reload register */
TMU->TSTR |= TMU_TSTR_STR0_Msk; /* Start counter */
INTC->IPRA &= ~INTC_IPRA_IPR_TMU0_Msk;
INTC->IPRA |= (1U << INTC_IPRA_IPR_TMU0_Pos); /* Interrupt priority 1 */
/* Wait until underflow occurs */
uint16_t tcr0 = 0U;
do {
tcr0 = TMU->TCR0;
} while ((tcr0 & 0x100) == 0);
while(s_tmu_flag != 1) {
asm("sleep");
}
TMU->TSTR &= ~1U; /* Stop counter */
s_tmu_flag = 0U;
TMU->TSTR &= ~TMU_TSTR_STR0_Msk; /* Stop counter */
}
int tuni0_handler(void) {
s_tmu_flag = 1U;
TMU->TCR0 &= ~(TMU_TCR_UNF_Msk);
return 0;
}

2
startup_stx7105.S
View File

@ -93,7 +93,7 @@ _exit_k:
_exc_base_k:
.long _exc_base
_exc_imask_k:
.long 0xFFFFFF0F /* Clear IMASK (SR[7:4]) to 0, enable all exception levels */
.long 0xEFFFFF0F /* Clear IMASK (SR[7:4]) to 0 and BL bit, enable all exception levels */
/*
* Exception handlers